Key responsibilities of the position are:
- Working with product engineers, customer support, and R&D to determine training requirements
- Creating and updating training lectures, labs, exams, and demos aligned with software and language standards releases and with high levels of quality
- Designing and developing lectures, labs, and demos that are deployed both online and in the classroom
- Delivering courses in a classroom or virtual setting
- Creating narrated online videos educating customers on how to use tools, languages, and methodologies
- Supporting online training customers when there are questions related to lectures and labs
A prospective candidate must have:
- A BSEE or MSEE degree
- Minimum 2 years of experience with SystemVerilog coding, UVM methodology projects, testbench creation, Simulation and Debug areas.
- Mandatory experience-exposure to low-power simulation and Functional safety simulation for at least 2 years
- Ability to author, analyze, and debug scripts in languages such as Bash, Perl, Python, and TCL
- Strong programming and HDL design and verification skills
- Ability to quickly analyze verification environments and design complexity
The selected candidate will:
- Excel at multitasking
- Expect to engage in a mixture of activities – authoring content, learning new tools and methodologies, “being the expert,” teaching and interacting with customers, and working with highly competent and experienced engineers.
- Given clear goals, work independently to accomplish such goals
- Have excellent written and verbal English communication skills
- Be well experienced using multimedia authoring tools, including Microsoft PowerPoint, Microsoft Word, and Adobe Acrobat and Photoshop (or equivalent), and audio/video tools such as Camtasia and Sound Forge.
- Be detail-oriented, well-organized, and receptive to challenges.
- Proactively react to resolve issues impeding progress
Skills Required
- BSEE or MSEE degree
- 2 years of experience with SystemVerilog coding
- Experience with UVM methodology projects
- Experience in low-power simulation and functional safety simulation
- Ability to author, analyze, and debug scripts in Bash, Perl, Python, TCL
- Strong programming and HDL design skills
- Excellent written and verbal English communication skills
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
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