SPE Verification Engineering

Posted 10 Hours Ago
Be an Early Applicant
Shanghai, Shanghai Municipality, Shanghai, CHN
In-Office
Senior level
Big Data • Internet of Things • Software
The Role
Own verification planning and execution for DDR memory interface products. Develop SystemVerilog and UVM testbenches, constrained-random tests, reference models, and coverage strategies. Debug issues, track bugs, contribute to verification methodologies, collaborate across engineering teams, and mentor junior engineers.
Summary Generated by Built In
Overview

As a Senior Principal Verification Engineer, the candidate will be reporting to the Director of Verification in this Full-Time position. Successful applicants will have a highly visible role in product development and take ownership of defining and executing verification plans for exciting DDR memory interface products.

Responsibilities
  • Create digital verification plans using datasheets, inputs from engineers/customers, and working closely with system and design engineers.
  • Implement digital test-benches in SystemVerilog and UVM to apply constrained random stimulus.
  • Implement UVM reference models to check digital DUT behavior.
  • Debug issues, Track bugs, functional coverage, and RTL code coverage
  • Work in a dynamic and interdisciplinary R&D group contributing to flow and methodology development
  • Mentor junior engineers

Qualifications
  • MS EE and 10+ years or PhD EE and 7+ years’ experience of Verification
  • Significant Experience with coding in System Verilog or Verilog and UVM methodology
  • Experience working in Analog/Mixed-signal products(DDR,HSS,PCIE etc.) is highly desirable
  • Significant Experience with standard ASIC Verification flow/software tools
  • Strong knowledge of scripting, Linux/Unix environment
  • Experience in leading and driving technical solutions across organization
  • The position requires good English written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams

Skills Required

  • MS in Electrical Engineering with 10+ years of verification experience
  • PhD in Electrical Engineering with 7+ years of verification experience
  • Significant coding experience in SystemVerilog or Verilog
  • Significant experience with UVM methodology
  • Significant experience with standard ASIC verification flow and software tools
  • Strong scripting knowledge
  • Strong knowledge of Linux or Unix environments
  • Experience leading and driving technical solutions across an organization
  • Strong written and verbal English communication skills
  • Ability to work effectively in cross-functional and globally dispersed teams
  • Experience with analog or mixed-signal products such as DDR, HSS, or PCIe
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The Company
HQ: San Jose, CA
989 Employees

What We Do

Dedicated to making data faster and safer, Rambus creates innovative hardware, software and services that drive technology advancements from the data center to the mobile edge. Our architecture licenses, IP cores, chips, software, and services span memory and interfaces, security, and emerging technologies to positively impact the modern world. We collaborate with the industry, partnering with leading chip and system designers, foundries, and service providers. Integrated into tens of billions of devices and systems, our products and technologies power and secure diverse applications, including Big Data, Internet of Things (IoT) security and much more!

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