Software Technical Program Manager

About the AI Division

The AI Division is a unique and dedicated group within Ceva, driving innovation in Machine Learning and Generative AI architectures for edge devices and cloud inference.

Our R&D domains span Neural Network Processors (NPU), Vision DSPs, and advanced AI algorithms for applications across smartphones, tablets, automotive, surveillance cameras and many more edge AI systems.

We combine cutting-edge hardware IP design with embedded software and system-level solutions, enabling the next generation of intelligent and energy-efficient devices.

About the Role:

In this role, as Software Technical Program Manager, you will serve as the central nervous system for the delivery of Ceva's NPU AI software stack, a complex, multi-layered system spanning the entire stack: from the graph compiler (frontend, middle-end, and backend) through the runtime, SDK, APIs, and UMD/KMD drivers on the Host, down to the embedded firmware on the NPU IP. You will own the planning, tracking, and delivery of the stack end to end, driving synchronization across the software engineering, software validation, and software architecture groups, managing external dependencies, and ensuring predictable milestone releases for both roadmap features and customer deliveries. Reporting to the Senior Director of Software, AI Division, you will be the consolidated interface of the software group towards Product, Program Management, VLSI & Simulator, CTO/Architecture, and Executive Leadership, translating commitments into an integrated, executable engineering plan. This is a matrix role with no direct reports: you will drive execution across the software groups through influence, clear commitments, and strong process ownership.

Responsibilities:

Unified Delivery Governance: Act as the single point of orchestration across the SW, SW Validation, and SW Architecture teams, aligning their independent schedules into one cohesive release timeline.

Cross-Group Synchronization: Host structured alignment syncs between STLs/TLs to lock down cross-component commitments and interfaces.

Strategic Interface: Serve as the primary, consolidated conduit for the SW group when interfacing with Product, Program Management, VLSI & Simulator, CTO/Architecture, and Executive Leadership.

Roadmap & Customer Milestone Mapping: Translate the Program Management POR, customer delivery commitments, and product requirements into actionable, integrated engineering milestones and plans across the software groups.

Preemptive Bottleneck Identification: Monitor resource and technical risks across the stack and flag early when one group's delay impacts the entire release.

Release Train Coordination: Drive the criteria for release readiness (Definition of Done) across the engineering, architecture, and validation groups.

Unified Post-Mortems: Lead comprehensive retrospective sessions after customer deliveries to optimize the co-development lifecycle between the groups.

SDLC Gatekeeper & Process Architect: Standardize and enforce unified quality gates, entry/exit criteria, and milestone definitions across the groups, ensuring seamless and predictable integration of the software stack.

• B.Sc. in Electrical Engineering, Computer Science, or a related field
• At least 5 years of experience as a Technical Program Manager, Project Manager, or Delivery Manager in a software or systems organization
• At least 5 years of hands-on software engineering background, with the technical depth to understand a multi-layered stack spanning compiler, runtime, driver, and firmware components, its internal interfaces and dependencies, and to challenge plans and estimations
• Proven track record of planning and delivering complex, multi-team software releases to committed dates, including external customer deliveries
• Experience defining and enforcing SDLC processes, quality gates, entry/exit criteria, and release readiness definitions
• Experience working with geographically distributed teams and sub-contractors
• Strong risk and dependency management skills, with the ability to identify bottlenecks before they impact the schedule
• Excellent leadership, communication, and interpersonal skills, with the ability to drive alignment and accountability without direct authority
• Strong English skills and the ability to drive execution in a fast-paced, matrixed environment

Advantages

• Experience with NPU, AI accelerator, or DSP software stacks
• Familiarity with graph/AI compiler and runtime frameworks (TVM, MLIR, IREE) or ML frameworks (TensorFlow, PyTorch, ONNX, TFLite)
• Experience in a semiconductor or IP company, including HW-SW co-development and silicon or IP release cycles
• Experience with embedded, firmware, or driver development environments (Linux, Android, RTOS)
• Hands-on experience with CI/CD, automated release processes, and Agile / Release Train methodologies
• Experience with program management and tracking tools (Jira, Azure DevOps, MS Project, or equivalent)
• M.Sc. in Electrical Engineering, Computer Science, or a related field, or a formal program management certification (PMP, SAFe, or equivalent)