Software Architect

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Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Software Architect – Virtual & Hybrid Platform Integration and Software Bring-up

Role Overview

We are looking for a seasoned Software Architect to join the team, responsible for Virtual and Hybrid platform integration and pre‑silicon software bring-up. The candidate will work on complex emulator- and FPGA-based platforms to enable early software development and validation for mobile, hyperscale, and automotive SoCs.

This is a hands-on individual contributor role requiring deep technical expertise, strong cross‑functional collaboration, and the ability to independently drive complex technical deliverables from architecture to execution.

Key Responsibilities

  • Architect, integrate, and debug Virtual and Hybrid platforms combining RTL, transactors, and virtual models for pre‑silicon enablement.
  • Develop systemC and Multithreaded C++ models and Transactors necessary for bringup of software on a Hybrid platform.
  • Lead software bring-up on pre‑silicon platforms (emulators / FPGA prototypes), including:
    • Bare‑metal environments
    • Linux OS
    • Android
    • Windows (where applicable)
  • Drive end‑to‑end platform readiness from early boot (ROM, bootloaders) to OS stability.
  • Work closely with RTL, IP, firmware, validation, and customer teams to define requirements, align interfaces, and plan deliverables.
  • Debug complex software and platform issues using:
    • Waveform analysis
    • Software debuggers (GDB, JTAG-based, emulator debuggers, etc.)
    • Logs and traces
  • Identify root causes across HW/SW boundaries and propose robust architectural fixes.

Technical Expertise & Qualifications

Required Skills

  • Strong background in software architecture with proven experience building and debugging complex pre‑silicon platforms.
  • Hands‑on experience integrating RTL with virtual and hybrid environments.
  • Deep understanding of SoC architecture and system-level behavior across:
    • Mobile
    • Hyperscaler / Datacenter
    • Automotive platforms
  • Expert knowledge of AMBA protocols and interconnects.
  • Proven experience working with and integrating key SoC IPs such as:
    • UFS, NVMe, PCIe
  • Strong proficiency in software debugging methodologies, including waveform-based debug and HW/SW co-debug.
  • Solid programming and scripting skills (C/C++, Python, shell scripting preferred).
  • Hands on experience on Multi-Threaded aspects, its challenges and tools to manage deadlocks

Preferred / Value-Add Skills

  • Experience with SystemC modeling and transaction-level modeling; ability to modify or develop models is a strong plus.
  • Prior experience working with emulators and FPGA-based platforms (Palladium, Protium, or similar).
  • Familiarity with GenAI / LLM-based workflows applied to EDA, debugging, automation, or productivity acceleration.
  • Knowledge of platform performance analysis and optimization.

Collaboration & Leadership Expectations

  • Strong ability to work across cross‑functional teams and with external customers to:
    • Understand complex, multi-team requirements
    • Translate them into executable technical plans
  • Ability to independently lead and execute projects, owning outcomes end to end.
  • While this is an individual contributor role, prior experience in:
    • Mentoring junior engineers
    • Technical leadership
    • Team or project ownership
      is highly valued.

Candidate Profile

  • A senior, hands-on technologist with strong problem-solving skills and a system-level mindset.
  • Comfortable operating in ambiguous, fast‑moving environments.
  • Motivated to align with long‑term technical growth and strategic platform evolution within Cadence.
We’re doing work that matters. Help us solve what others can’t.

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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