SOC DFT Engineer

Job Details:

Job Description: 

• Develop and implement DFT strategies and methodologies for complex SOC designs.
• Perform static and dynamic test pattern generation (ATP) to ensure comprehensive test coverage for designs.Work with design, verification, and manufacturing teams to define test requirements and integrate DFT features into designs.
• Optimize design testability, ensuring minimal test time while maximizing fault coverage.
• Lead and mentor junior DFT engineers, providing guidance and technical leadership.
• Support post-silicon validation by ensuring that the designs meet the required test coverage and quality.
• Collaborate with hardware engineers to ensure that testability and manufacturing testability requirements are met.
• Develop DFT-related automation tools to improve efficiency and streamline processes.
• Perform advanced DFT design and implementation on techniques such as boundary scan, scan compression, BIST (Built-In Self-Test), and JTAG.
• Analyze test coverage and suggest improvements to ensure optimal test coverage.
• Provide DFT analysis and reporting to both internal teams and external clients.
• Work closely with the manufacturing team to ensure designs are optimized for testability, yield, and cost.

Qualifications:

Minimum Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
• 5+ years of experience in DFT, SOC design, or related semiconductor design areas.
• Strong knowledge of DFT techniques, including scan insertion, BIST, boundary scan, JTAG, and fault simulation.
• Experience with EDA tools for DFT (e.g., Synopsys DFT Compiler, Mentor Tessent, Cadence Modus, ATPG).
• Proficiency in hardware description languages such as VHDL, Verilog, or SystemVerilog.
• Expertise in automated test generation and analysis tools.
• Strong problem-solving skills with the ability to troubleshoot complex testability issues.
• Experience with RTL design and verification processes.
• Excellent communication and teamwork skills to collaborate with multi-disciplinary teams.
• Ability to analyze, review, and optimize existing DFT strategies for design and test coverage.
• Familiarity with semiconductor manufacturing processes and test flows.

Preferred Qualifications:

• Experience with advanced test techniques such as DFT for low-power designs.
• Familiarity with industry standards such as IEEE 1687 (IJTAG), 1149.1 (JTAG), IEEE 1500 (Core Test), and others.
• Knowledge of Python or other scripting languages for automation.
• Experience with failure analysis, yield improvement and test cost optimization methodologies.
• Experience with SOC (System on Chip) or complex multi-chip designs

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:Experienced Hire

Shift:Shift 1 (Malaysia)

Primary Location: Malaysia, Penang

Additional Locations:Malaysia, Kulim

Business group:The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.