Phizenix

SOC Design Verification Engineer

Reposted Yesterday

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Santa Clara, CA, USA

In-Office

160K-180K Annually

Senior level

Artificial Intelligence • Information Technology • Consulting

Talent Solutions for the AI Era

The Role

Develop and maintain UVM-based verification environments for SoC designs, including writing SystemVerilog assertions, debugging, and collaborating on verification plans.

Summary Generated by Built In

We are seeking an experienced SoC Design Verification Engineer with a strong background in UVM-based verification and SystemVerilog to join our dynamic engineering team. The ideal candidate will have hands-on experience in developing and executing complex verification environments, integrating C/C++ models, and debugging issues at both IP and subsystem levels.

Key Responsibilities:

Develop, implement, and maintain UVM-based verification environments for SoC and IP-level designs.
Write and execute SystemVerilog assertions to validate design functionality and performance.
Integrate C/C++ reference models within verification testbenches and ensure seamless co-simulation.
Perform debugging at IP and subsystem levels, identifying and resolving functional and timing issues.
Collaborate with design, architecture, and validation teams to define verification plans, strategies, and coverage goals.
Review and analyze waveforms, simulation logs, and coverage reports to ensure thorough verification closure.
Participate in regression management, bug tracking, and documentation for design verification deliverables.

Required Qualifications:

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
10+ years of hands-on experience in SoC or IP-level design verification.
Strong proficiency in SystemVerilog, UVM methodology, and assertion-based verification (ABV).
Experience integrating C/C++ models in verification environments.
Proven debugging skills at both IP and subsystem levels using industry-standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, or Mentor Questa).

Good to Have:

Gate-Level Simulation (GLS) and post-silicon verification exposure.
Experience with Low Power Verification (UPF / CPF) methodologies.
Familiarity with ARM-based SoC architectures and interconnect verification.

California Pay Range

$160,000—$180,000 USD

Top Skills

C/C++

Cadence Xcelium

Eda Tools (E.G.

Mentor Questa)

Synopsys Vcs

Systemverilog

Uvm-Based Verification

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The Company

HQ: Livermore, CA

9 Employees

Year Founded: 2025

What We Do

We provide Talent Solutions for the AI Era. Our mission is to connect businesses with exceptional talent and consulting solutions that align with your company’s culture and values. We offer AI consulting services to enable businesses in leveraging cutting-edge artificial intelligence. We help discover, design and deploy AI solutions that streamline operations, boost productivity, and unlock new growth opportunities. Our team of AI experts, strategists, and technology specialists work closely with organizations to integrate AI-driven solutions that align with their unique goals and challenges. From automation and data analytics to predictive modeling and AI-based customer experiences, we provide end-to-end support for businesses embarking on their AI transformation journey.