SOC Design Engineer/Lead

Job Details:

Job Description: 

Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the AI SOC / CPU IP block for integration in full chip designs. Participates actively in the definition of architecture and microarchitecture features of the AI SOC/CPU being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure high quality integration of the CPU block.

Qualifications:

Minimum Qualifications:

Bachelor's with 13+ Years and Master's with 10+ Years of relevant experience in the semiconductor industry.

10+ years of experience in/with: Verilog and system Verilog, synthesizable RTL Modern design techniques and energy-efficient/low power logic design and power analysis.

5+ years of experience in/with: Having achieved multiple tape-outs reaching production with first pass silicon.

Hands on experience with FPGA emulation, silicon bring-up, characterization and debug.

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Business group:Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.