SoC Design Engineer - Manual Debug Team

Job Details:

Job Description: 

Come join Intel's Design Development Group organization as an SOC Manual Debug Team engineering focused on speeding up post silicon debug of our latest client CPUs. As a member of the product team, you will work firsthand with multi-function teams/sites, to bring design expertise into helping debug and enabling our most advanced client CPUs in post-Silicon and product launch.

In this role you will be working as part of a pre-silicon on architecture, design and validation of new features and as part of the post-silicon team to help speed-up sighting debug, feature enabling, product PnP tuning and customer enabling. You will be working with pre-silicon and post -silicon validation teams to feedback learnings to improve design quality and debug visibility. You will also work closely with post-silicon validation SW teams on debug tool validation, sighting debug and silicon enabling.

Your responsibilities will include but not be limited to:

• Defining new debug feature to help speed up post-si enabling of complex features and flow.
• Enabling debug tools and scripts to speed up sighting failure analysis and root-causing.
• Focusing on debugging some of the most critical post-si sightings to speed up our product Power-On and volume validation.
• Pre Silicon validation of functional and debug features in simulation, emulation and/or FPGA to ensure less issues are seen in post-si enabling
• Creating test plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide
• Learning the Power Management, Memory and debug architecture and microarchitecture by debugging failures to the root cause.
• Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design
• Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models
• Feedback back post silicon learnings into design to make more robust architecture and/or features
• Developing debugging tools and software

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Candidate must have either a BS or MS in Computer Science, Computer Engineering or Electrical Engineering.
• 8+ years of experience with the following:  
  • Pre-silicon and Post-silicon enabling, driving sighting debug and closure, debug tools.
  • Working across validation, architecture, SW, and design teams to resolve debug issues.
  • HW, FW and SW Interaction and debug to root cause.
  • Computer architecture.

 Preferred Qualifications

• Writing validation plans and software to implement those validation plans.
• Reading and interpreting technical specs and Register Transfer Level (RTL) code.
• Programming languages/Scripting: C, Perl, Verilog and UNIX or Linux.
• 8yrs+ experience with validation or testing experience, especially in a silicon design team.
• 6yrs+ experience with IA-32 assembly and/or Verilog programming experience.
• 6yrs+ experience with industry standards such as ATB, Core sight, JTAG.

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations:

Business group:In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations.  DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$186,070.00-$262,680.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.