Sr. Memory Designer

Posted One Month Ago
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San Jose, CA, USA
In-Office
248K-248K Annually
Expert/Leader
Semiconductor • Manufacturing
The Role
Leads SoC and chiplet-based MCM development from architecture through tapeout and production. Owns chip signoff, system-level modeling, performance tradeoffs, debug, DFx methodology, and hardware design decisions across processor, memory, interconnect, security, configuration, and high-speed interface subsystems. Provides technical leadership across distributed engineering teams, manages IP vendor roadmaps, supports emulation and validation, presents technology strategies to executives, and applies agentic AI to accelerate design execution.
Summary Generated by Built In
Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description:

Sr. Memory Designer

Key Responsibilities:

  • Design and Development: Lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM)

  • Architecture and Implementation: Develop memory architectures and implement them in advanced semiconductor technologies, including FinFET and nanometer CMOS

  • Simulation and Verification: Perform schematic capture, simulation, and margin verification of major memory blocks

  • Layout Planning: Oversee layout planning and ensure tight pitch-matched memory layout designs

  • Collaboration: Work closely with architecture and design teams to define memory PPA (Performance, Power, Area) and yield targets

  • Full Design Flow: Manage the full embedded memory design flow, including architecture, circuit design, physical implementation, compiler usage, characterization, timing, and model generation

  • Innovation: Bring innovative and revolutionary ideas to life in our products, influencing various parts of our FPGA designs

Qualifications:

  • Education: Bachelor’s degree in electrical engineering, or a related field. A Master’s or PhD is preferred

  • Experience: Over 10 years of experience in memory design, verification, validation, and integration

  • Technical Skills:

    • Strong knowledge of custom memory design, high speed, low power as well as custom memory design for configuration of FPGA

    • Expertise in high-performance and low-power design techniques

    • Familiarity with variation-aware design in advanced semiconductor technologies

  • Soft Skills: Excellent problem-solving skills, strong communication abilities, and the ability to work collaboratively in a team environment

Preferred Qualifications:

  • Experience with large density memory cell design for high yield

  • Knowledge of semiconductor device fundamentals

Pay & Benefits

Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. 

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

220800

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. 


Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit 
www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.

 

As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.

Skills Required

  • BS, MS, or PhD in Electrical Engineering or Computer Engineering
  • 20+ years of FPGA or SoC design experience
  • Track record leading programs from concept through tapeout and production release
  • Expertise in SystemVerilog, synthesis, and static timing analysis
  • Expertise in high-speed interfaces, system interconnects, processor subsystems, and 2.5D/3D packaging and chiplet architectures
  • Experience with system-level functional and performance modeling, RTL correlation, and emulation-based pre-silicon validation
  • Experience defining and owning DFx methodology, including scan, BIST, and manufacturing test
  • Experience debugging complex use cases through verification, emulation, and system validation
  • Ability to lead and grow geographically distributed, cross-functional engineering teams
  • Strong written and oral communication skills with executive-level presentation experience
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The Company
HQ: Hillsboro, OR
975 Employees
Year Founded: 1983

What We Do

Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world. Lattice was founded in 1983 and is headquartered in Hillsboro, Oregon with major operations in San Jose, California, Shanghai, China, and Manila, Philippines.

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