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The Role
Lead cross-functional efforts to advance circuit simulation and modeling for advanced foundry technologies. Partner with EDA vendors to enhance and validate simulation tools and flows, align capabilities with technology and VLSI physical design roadmaps, and drive readiness of high-quality simulation and modeling solutions for timely PDK delivery.
Summary Generated by Built In
Job Details:Job Description:
Annual Salary Range for jobs which could be performed in the US: $173,660.00-284,580.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
In this role, you will lead cross-functional collaboration to advance circuit simulation and modeling capabilities for advanced foundry technologies.
Your responsibilities will include:
- Vendor collaboration: Partnering with EDA vendors to enhance and validate industry-standard simulation tools and design flows.
- Technology alignment: Working closely with technology leaders, VLSI physical design teams, and PDK teams to ensure simulation and modeling capabilities are aligned with roadmap needs.
- PDK readiness: Driving readiness of high quality simulation and modeling solutions so they are available in time for PDK delivery.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
- Bachelor’s degree in electrical engineering or computer engineering or related engineering discipline with 12+ years or master’s degree in electrical engineering or a related discipline and at least 10 years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline with a minimum of 8 years of industry experience in the semiconductor field.
- 5+ years supporting circuit simulation tools and working with circuit simulation vendors to develop solutions.
- 5+ years collaborating with EDA vendors on optimizing circuit simulation and modeling for advanced technology nodes.
- 3+ years of hands-on experience with BSIM or other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA).
- 5+ years of comprehensive understanding of compact modeling, simulation methodologies used by digital and analog designers, aging modeling and methodologies and modeling interfaces to simulation tools like OMI.
Preferred Qualifications
- Demonstrated experience in technical leadership and Proven capability to collaborate across multiple teams and geographies.
5+ years of experience in leading technical teams in the areas of simulation and modeling. - Exceptional leadership skills with focus on collaboration and finding solutions.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $173,660.00-284,580.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's degree in electrical engineering or computer engineering or related engineering discipline with 12+ years OR Master's degree in electrical engineering or related discipline with at least 10 years OR Ph.D. in Electrical Engineering or related discipline with minimum of 8 years industry experience in the semiconductor field.
- 5+ years supporting circuit simulation tools and working with circuit simulation vendors to develop solutions.
- 5+ years collaborating with EDA vendors on optimizing circuit simulation and modeling for advanced technology nodes.
- 3+ years hands-on experience with BSIM or other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA).
- 5+ years comprehensive understanding of compact modeling, simulation methodologies used by digital and analog designers, aging modeling and methodologies and modeling interfaces to simulation tools like OMI.
- 5+ years of experience in leading technical teams in the areas of simulation and modeling.
- Demonstrated technical leadership and proven capability to collaborate across multiple teams and geographies.
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
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