Silicon Physical Design Verification Manager

Posted 11 Days Ago
Be an Early Applicant
2 Locations
Hybrid
7+ Years Experience
Software
The Role
Join a hardware startup in Silicon Valley as a Silicon PDV Engineering Manager responsible for developing PDV methodology, driving convergence, performing full chip integration, and managing a team of engineers. Must have deep understanding of advanced process nodes, experience in full chip convergence for high-end chip designs, and strong scripting skills in tcl and python.
Summary Generated by Built In

Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Silicon PDV Engineering Manager. Our mission is to reimagine silicon and create Risc-V based computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

Responsibilities

  • Develop PDV methodology and infrastructure to enable the verification flow of large SoCs across DRC, LVS, ESD.
  • Drive convergence across analysis types at full chip level and sub blocks.
  • Perform full chip integration and run the complete suite of physical verification checks
  • Provide guidance to the implementation teams throughout the project to enable early convergence and final closure
  • Interface with various internal and external design teams to ensure the high quality of their deliverables and successful integration
  • Work with the package and floorplan teams to define padring and bump map design
  • Collaborate with our technology team to define flows and integrate foundry PDK data
  • Manage a team of engineers to deliver PDV convergence to meet or exceed program milestones.

Requirements

  • Deep understanding of the challenges associated with advanced process nodes (7nm and below).
  • More than 10 years experience in managing and driving full chip convergence for high end chip designs using advanced process nodes.
  • Hands-on experience with auditing rule decks and settings to drive convergence.
  • Hands-on experience in closure and tapeout of large hierarchical designs.
  • Experience with industry standard physical verification tools (Calibre, Pegasus)
  • Strong scripting skills in tcl and python
  • Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
  • Self starter and highly motivated
  • Ability to work cross-functionally with various teams and be productive under aggressive schedules
  • Good written and verbal communication skills.

Education and Experience

 Masters + 15 years experience.

Top Skills

Python
Tcl
The Company
HQ: Mountain View, CA
287 Employees
On-site Workplace
Year Founded: 2021

What We Do

Rivos, a high performance RISC-V System Startup targeting integrated system solutions for Enterprise

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