Silicon Design Engineering Manager – AI SoC Deployment

Job Details:

Job Description: 

Join Intel’s strategic AI initiative and lead a team building next-generation AI SoC. In this role, you will drive the design and development of advanced silicon for AI workloads, lead a talented engineering team in a fast-paced, startup-mode environment, collaborate across architecture, verification, and software teams to deliver breakthrough performance and Influence Intel’s AI roadmap and shape industry standards.

What We’re Looking For:

• Proven leadership in silicon design and team management.
• Expertise in RTL design, microarchitecture, and performance analysis.
• Passion for innovation and ability to thrive in an agile environment.

Key Responsibilities:

• Lead and manage a team of senior engineers, including Senior Chip Design Engineers, SoC verification , and SoC Integration Engineers.
• Oversee the design, development, integration, and verification of complex digital hardware (RTL using Verilog/SystemVerilog) with a focus on Power, Performance, and Area (PPA) for System-on-Chips (SoCs).
• Ensure seamless collaboration and IP integration across global teams, maintaining high standards of quality.
• Guide the development and deployment of high-performance, production-ready AI systems using machine learning frameworks such as PyTorch and Large Language Models (LLMs).
• Drive the design of high-performance, power-efficient silicon tailored for machine learning and deep learning workloads, bridging the gap between traditional hardware engineering and modern AI software frameworks.
• Manage the integration of various intellectual property (IP) blocks into functional chips optimized for AI tasks.

Qualifications:

• Proven experience in leading and managing technical teams.
• Strong background in digital hardware design, machine learning frameworks, and AI system deployment.
• Excellent leadership and communication skills, with the ability to inspire and motivate a team of top-tier engineers.
• Demonstrated expertise in SoC architecture, IP integration, and post-silicon validation processes.
• Ability to collaborate effectively with global teams and stakeholders, ensuring the successful delivery of complex projects.

Preferred Qualifications:

• Advanced degree in Electrical Engineering, Computer Science, or a related field.
• Experience working with Verilog/SystemVerilog, PyTorch, and Large Language Models (LLMs).
• Familiarity with RISC-V cores and networking blocks.
• Strong scripting and verification skills for high-speed chip design.

          

Job Type:Experienced Hire

Shift:Shift 1 (Israel)

Primary Location: Israel, Haifa

Additional Locations:

Business group:At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.