Leads silicon design efforts for SASIC, including logic design, design verification, circuit design, and physical design. Owns the delivery of high‑quality IPs, subsystems, SoCs, and/or discrete silicon products while driving excellence in execution, silicon quality, and engineering productivity.
Responsibilities
Work with customer facing teams to debug verify, circuit, and physical design to deliver complex IPs, subsystems, SoCs, or discrete chips.
Conduct and oversee architecture and design reviews to ensure power, performance, area, cost (PPAC), and quality targets are met.
Drive continuous improvement of silicon development methodologies, design processes, and architectural definition across design disciplines.
Oversee design verification strategy and execution, including test results review, data analysis, issue tracking, root cause analysis, and corrective action implementation.
Partner closely with IP, platform, and SoC teams to enable integration, performance optimization, and robust design implementation.
Establish clear goals and milestones, remove execution barriers, maintain accountability, and drive predictable delivery outcomes.
Apply effective performance management, coach and develop talent, and foster a collaborative, high‑performance engineering culture.
Minimum Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
Proven experience in silicon design across one or more domains: logic design, verification, circuit design, or physical design.
Experience leading technical teams or projects in semiconductor or silicon product development.
Strong understanding of full silicon development lifecycle, from architecture definition through tape‑out and post‑silicon validation.
Demonstrated ability to drive quality, execution discipline, and cross‑functional collaboration.
Preferred Qualifications
Master’s degree or PhD in Electrical Engineering or related field.
Experience leading multi‑disciplinary teams delivering complex SoC or IP designs at advanced process nodes.
Deep knowledge of PPAC optimization, silicon bring‑up, debug, and yield considerations.
Strong data‑driven decision‑making skills and experience driving process and methodology improvements.
Excellent communication, leadership, and stakeholder management skills.
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