The Role
The role involves verifying digital design blocks, building verification environments using SystemVerilog and UVM, and collaborating with design engineers to ensure full functionality coverage.
Summary Generated by Built In
For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Senior Verification Engineer to be driving into the complicated RTL design verification activity on various design aspects.
Key responsibilities:
- Ownership of block\cluster verification end to end from scratch.
- Lead efforts of test bench architecture, Vplan definition and functional coverage.
- Work closely with the design, architecture, algo teams and other stakeholders.
- Support other team members and mentor less experienced engineers.
Requirements
- 10+ years of experience – a must
- Performed at last 2 or more full block/system verification cycles.
- In depth knowledge in VLSI verification flow, languages and concepts.
- Experience in data path or data protocols, specifically Ethernet - preferred
- Verification using one of the known methodologies (eRM, UVM).
Responsibilities
- Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.
- Build verification environments using SystemVerilog and UVM.
- Identify and write all types of coverage measures for corner-cases.
- Debug the functionality with design engineers.
- Perform coverage collection and follow the metrices to close the full functionality.
Top Skills
Erm
Ovm
Systemverilog
Uvm
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The Company
What We Do
We are a semiconductor startup that has brought together a world-class team of ASIC designers, optical communications experts and seasoned investors that excel at creating disruptive technologies.
Together, we are building a novel semiconductor technology that will transform the datacenter and telecommunications industries.
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