Senior Timing and Constraints Methodology Engineer

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and SoCs. In this role, you’ll develop methodology and flows to validate timing constraints from RTL to netlist via structural, functional and cross-hierarchy constraints checks. We're looking for someone passionate about the challenges of designing most complex deep sub-micron design (3nm and beyond) who thrives on pushing the limits of precision and scalability. You’ll collaborate across teams to shape methodologies that influence the entire future of computing.

What you will be doing:

• Develop mythologies and flows to validate constraints with industry-standard tools (e.g., PrimeTime, SNPS TCM ) and debug anomalies in timing reports.

• Support tapeout-quality STA environments that are scalable, reusable, and validated through both structural and formal processes for constraint correctness

• Analyze RTL clock constructs to derive clock definitions and relationships for timing analysis.

• Interpret hierarchical clock structures, including clock cell usage and propagation paths, to build signoff-accurate timing environments.

• Write automation scripts in Perl, Python, and C++ for constraint generation, validation, and structural checks.

• Create and enforce clock-related structural checks (e.g., valid crossing of clock domains across hierarchical boundaries).

• Collaborate with RTL, physical design, and verification teams to drive consistency and correctness across design stages.

What We Need To See:

• MS (or equivalent experience) in Electrical or Computer Engineering with 4+ years’ experience in ASIC Design and Timing.

• Expertise in Primetime and timing constraints

• Knowledge of device physics, STA methodology.

• Exposure to RTL to GDSII flows

• Good understanding of mathematics/physics fundamentals of electrical design.

• Expertise in coding- TCL, Python. C++

• Strong communications skill and good standout colleague

NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.Applications for this job will be accepted at least until July 29, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.