We are seeking an experienced SystemC Engineer to join our ASIC development team. The ideal candidate will have a strong background in SystemC modeling, digital signal processing (DSP), and ASIC development flows. This role involves developing high-level SystemC models, translating DSP algorithms into efficient SystemC implementations, and working closely with architecture, System, RTL, verification, and algorithm teams to enable system-level modeling and verification.
Requirements
Responsibilities
* Develop and maintain high-performance SystemC models for complex optical systems and ASIC designs.
* Translate DSP algorithms from MATLAB into accurate and efficient SystemC implementations.
* Translate optical systems modeling into SystemC models
* Collaborate with architecture, RTL, and verification teams throughout the ASIC development lifecycle.
* Develop executable reference models for architecture exploration and functional validation.
* Support verification environments by integrating SystemC models into mixed-language simulation environments.
* Analyze and optimize model performance while ensuring functional accuracy.
* Debug and resolve functional issues across system-level.
* Participate in architecture definition, design reviews, and technical discussions.
Required Qualifications
* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
* Minimum 5 years of experience in SystemC development.
* Strong proficiency in SystemC, C++, and Transaction-Level Modeling (TLM).
* Experience with ASIC design and verification environments.
* Experience translating DSP algorithms from MATLAB to SystemC.
* Knowledge of digital signal processing concepts and fixed-point arithmetic.
* Hands-on experience with communication interfaces, including:
* Ethernet
* DSP-based communication systems
* Optical links/high-speed serial interfaces
* Strong debugging, analytical, and problem-solving skills.
* Excellent communication skills and ability to work in cross-functional engineering teams.
Preferred Qualifications
* Experience with UVM and SystemVerilog verification environments.
* Familiarity with RTL design (Verilog/SystemVerilog/VHDL).
* Experience with high-speed networking or communication ASICs.
* Knowledge of scripting languages such as Python or Perl.
* Experience with performance modeling and architectural exploration.
* Familiarity with version control systems (Git) and continuous integration workflows.
Desired Skills
* Strong system-level thinking and architectural understanding.
* Ability to work independently while collaborating across multidisciplinary teams.
* Attention to detail with a focus on model accuracy and maintainability.
* Passion for solving complex technical challenges in ASIC and communication system development.
Skills Required
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Minimum 5 years of experience in SystemC development
- Strong proficiency in SystemC and C++
- Experience with Transaction-Level Modeling (TLM)
- Experience with ASIC design and verification environments
- Experience translating DSP algorithms from MATLAB to SystemC
- Knowledge of digital signal processing concepts and fixed-point arithmetic
- Hands-on experience with communication interfaces: Ethernet, DSP-based communication systems, optical links/high-speed serial interfaces
- Strong debugging, analytical, and problem-solving skills
- Excellent communication skills and ability to work in cross-functional engineering teams
- Experience with UVM and SystemVerilog verification environments
- Familiarity with RTL design (Verilog/SystemVerilog/VHDL)
- Experience with high-speed networking or communication ASICs
- Knowledge of scripting languages such as Python or Perl
- Experience with performance modeling and architectural exploration
- Familiarity with version control systems (Git) and continuous integration workflows
Retym Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Retym and has not been reviewed or approved by Retym.
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Fair & Transparent Compensation — Pay is positioned as a relative bright spot compared with broader company sentiment, with compensation rated more favorably than overall sentiment in the available snapshot.
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Strong & Reliable Incentives — Good incentives are described alongside work-life balance in one public summary, suggesting rewards may be a meaningful part of the package for some employees.
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Wellbeing & Lifestyle Benefits — Meal support is implied by mention of Grubhub among “pros,” indicating at least some lifestyle/perk coverage may exist for certain teams or locations.
Retym Insights
What We Do
We are a semiconductor startup that has brought together a world-class team of ASIC designers, optical communications experts and seasoned investors that excel at creating disruptive technologies. Together, we are building a novel semiconductor technology that will transform the datacenter and telecommunications industries.
