Senior Staff SW QA Engineer (FPGA Tool)

Posted Yesterday
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Penang, Daerah Timor Laut, Penang, MYS
In-Office
Senior level
Semiconductor • Manufacturing
The Role
Lead design and development of Lattice FPGA software tools in Penang, focusing on FPGA primitives, Foundation IP and IP catalog tooling. Own release cycle planning, requirement analysis, feature scoping, development, testing and validation. Provide technical leadership, mentor engineers, and ensure delivery quality. Hands-on RTL, testbench, verification, timing closure, device modeling and EDA tool development using C++ and Python.
Summary Generated by Built In
Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description:

We are looking for a highly skilled and experienced Software QA Test Engineer to join our dynamic team. The ideal candidate will possess a robust background in validating software tools along with proficiency in Verilog, System Verilog and VHDL. You will play a pivotal role in the verification in our software tools and foundation IP using cutting edge methodologies and tools.

Responsibilities:

  • Validate FPGA design flows (compilation, simulation, power, timing, bit stream) that are closely integrated with FPGA IP.

  • Develop, maintain and enhance test plans for FPGA IP blocks and software verification tools.

  • Write and execute test cases for functional and performance verification of FPGA IP blocks.

  • Validate FPGA IP catalog to ensure intuitive and error-free to user interfaces.

  • Analyze coverage metrics and refine test scenarios to achieve coverage goals.

  • Review, collaborate and analyze feature requirements with stakeholders.

Education

  • Bachelor’s or Master’s degree in Electronic Engineering, Computer Science, Software Engineering, or related fields.

Experience:

  • 12+ years of experience in software/IP testing and quality assurance with a proven track record in IP block verification.

  • Hands-on experience writing and executing test cases for functional and performance verification of FPGA IP blocks.

  • Proficient in Verilog, System Verilog and VHDL.

  • Knowing UVM is a plus.

  • Solid experience in Simulation/Verification using VCS, Questa, power, timing, IBIS analysis of FPGA design flows.

  • Knowledge in FPGA architecture and silicon features such as SERDES and DDR is a plus.

  • Familiarity with GUI testing frameworks and tools such as Squish is a plus.

  • Ability to work independently and drive tasks to completion.

  • Capable of providing technical guidance and code reviews to junior engineers.

Soft Skills:

  • Strong analytical and problem-solving abilities.

  • Excellent verbal and written communication skills.

  • Effective collaboration and stakeholder management skills.

  • Detail-oriented and proactive in identifying quality issues.

  • Creative and innovative mindset.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Malaysia

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. 


Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit 
www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.

 

Skills Required

  • Bachelors, Masters or better in Computer Science, Computer Engineering, Electrical Engineering, or related fields
  • 12+ years of experience in EDA software tool development
  • Strong communication skills
  • Knowledge or experience in FPGA architecture and FPGA software tools (device modeling and soft IP development)
  • Programming skills in C++ and Python
  • Hands-on experience in FPGA RTL design, testbench development, logic verification, timing closure and debugging
  • Expertise in multi-domain FPGA primitives (embedded block RAM, DSP blocks, PLL, oscillators, I/O gearing, configuration/security, power-related silicon features)
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The Company
HQ: Hillsboro, OR
975 Employees
Year Founded: 1983

What We Do

Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world. Lattice was founded in 1983 and is headquartered in Hillsboro, Oregon with major operations in San Jose, California, Shanghai, China, and Manila, Philippines.

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