Senior Staff Engineer, Physical Design

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

What You Can Expect

As a key member of central physical design team, you will provide backend design service for multiple Marvell SOC design groups, from floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff to physical verification (DRC/LVS/Antenna). You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed SOCs. You will work closely with frontend and integration team to ensure successful tapeouts. Your responsibility may include participating in cutting-edge physical design methodology and flow development.

What We're Looking For

• BS/MS in EE/CS with 6+ years of hands-on experience in CAD back-end physical design and verification.

• Familiar with hierarchical physical design strategies, methodologies and deep sub-micron technology issues like 7nm, 5nm and below. Familiar with ASIC design flow, Verilog HDL, synthesis and timing closure.

• Proven track records of handling chip level P&R independently and taping out complex SOC chips under tight schedule pressure.

• Must be programming-minded, solid coding experience in Makefile/Tcl/Perl/Python.

• Detail oriented, self-motivated team worker, good verbal and written communication skills.

• Must be a power user of Cadence suite (Genus, Innovus), Synopsys suite (Fusion Compiler, IC Compiler).

• Solid knowledge on static timing analysis (Tempus, PrimeTime), EM/IR-Drop/crosstalk analysis (Voltus, PTSI, Redhawk), extraction (QRC, StarRC), formal or physical verification (LEC, Formality, Calibre, ICV) a plus.

• Good communication skills and self-discipline contributing in a team environment.

Expected Base Pay Range (USD)

121,840 - 182,500, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].

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