As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
Key Responsibilities:
Lead the verification and optimization of our diverse RISC-V Low Power Profiles, including UPF.
Drive and achieve quality closure targets at both the CPU and block levels.
Collaborate closely with microarchitecture and RTL design teams to optimize complex Power flows.
Provide technical leadership and mentorship to junior team members to foster team growth and enrichment.
Actively participate in the test planning and execution phases for new architecture and design features.
Requirements
10+ Years of experience in low power or power aware or power management
Experience with hands on UVM Test Bench development is must
Experience in core uArch is highly desirable.
Experience in leading effort and driving multiple projects
Experience with power simulation on vcs and upf.
Experience with script writing in Python, Perl or Tcl.
Experience with power impact at architecture, logic design, and circuit levels.
Excellent problem solving skill and ability to work in a dynamic and diverse environment.
Qualification:
A minimum of bachelor’s or master’s Degree, or equivalent in Electrical & Electronic Engineering or Electrical & Communication Engineering or VLSI with consistently good academics
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Skills Required
- 10+ years of experience in low-power, power-aware, or power-management engineering
- Hands-on experience developing UVM testbenches
- Experience leading efforts and driving multiple projects
- Experience with power simulation using VCS and UPF
- Experience writing scripts in Python, Perl, or Tcl
- Experience analyzing power impact at architecture, logic-design, and circuit levels
- Bachelor’s or master’s degree, or equivalent, in Electrical and Electronic Engineering, Electrical and Communication Engineering, or VLSI
- Experience with core microarchitecture
- Excellent problem-solving skills and ability to work in a dynamic, diverse environment
What We Do
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
