Senior Digital Design Engineer (MS-50021164)

Responsibilities:

• Develop CMOS mixed-signal circuitry through all phases of development from concept to production release.
• Model control loops and signal processing algorithms using tools such as Matlab and Simulink
• Implement and integrate digital IP such as digital communication interfaces, state machines, A/D interfaces, digital arithmetic, digital filters, and digital feedback control loops in Verilog or SystemVerilog HDL languages
• Collaborate in functional verification of your digital IP and behavioral modeling of analog and mixed signal circuits.
• Collaborate in physical design process including identifying timing constraints, reviewing static timing analysis, running gate-level simulations and doing digital power analysis
• Evaluate, learn, and debug devices in the lab after design.
• Support post-silicon activities including product validation, characterization, and production test.

Required Skills and Experience:

• Degree in Electrical, Electronics, Computer Engineering, or a closely related field; Bachelors with 5+ yrs of relevant experience, Masters with 3+ yrs of relevant experience, or PhD with 0+ yrs experience.
• Deep understanding of the digital design flow steps including architecture, design, validation, and design integration.
• Experience in using Verilog or SystemVerilog to implement digital communication interfaces, state machines, A/D interfaces, digital arithmetic, digital filters, and digital feedback control loops.
• Experience in using Verilog or SystemVerilog to do functional verification of digital IP blocks in mixed-signal environment.
• Solid understanding of high-level modeling tools such as Matlab, Simulink, or similar.
• Understanding of control theory and discrete time, z-domain, signal processing techniques.
• Hands-on lab test/debug experience.
• Strong collaboration through oral and written communication.
• Strong analytical and problem-solving skills.

Preferred Skills and Qualifications:

• Experience with MCU or DSP processor based SoC architectures.
• Experience with back-end flow including synthesis, place and route, and timing analysis.
• Experience generating functional test vectors for PTE.