Senior Staff Design Verification Engineer - SOC

We are seeking an experienced Senior Staff Verification Engineer. This position involves extensive hands-on experience with CPU verification using industry-standard functional verification methodologies, formal verification and constrained random generators, and reference model-based checkers. The candidate must be able to take critical decisions and completely own verification closure for a block or feature. This position involves cross-functional interaction with CPU designers and architects and working across sites to ensure high-quality CPU designs for customers. 

You will:

• Take full ownership and drive verification efforts to closure 
• Work closely with designers and architects to understand specifications at unit/top level 
• Understand use cases and develop functional test plans 
• Develop directed tests written in C, Assembly, and SystemVerilog 
• Develop random test generators to stress microarchitectural implementations 
• Analyze coverage and fix holes in the test plan 
• Enhance the verification environment and testbench using the latest methodologies, tools, and automation 
• Support for prototyping in FPGA and/or Emulation 

Ideally, you’ll have:

• Bachelor’s or Masters's degree preferred in Electronics/Electrical/Computer Engineering or equivalent field with 8+ years of industry experience with a focus on functional verification in SOC (System on Chip) verification. 
• Familiarity with heterogenous multi-core, AMBA and high-speedIO architectures and industry-leading RISC or Arm processors 
• Exposure to various EDA design verification tools with good digital design concepts 
• Knowledge and experience with Interconnect protocols like AXI/ACE/OCP/CHI 
• Scripting experience in Python/Perl/TCL/Shell 
• Experience in creating functional test plans and implementing them as part of pre-silicon verification 
• Strong knowledge of Verilog/SystemVerilog/C/C++/Assembly 
• Strong analytical and problem-solving skills 
• Are self-motivated with excellent communication and presentation skills, and the ability to collaborate well with local and global teams 

A plus if you have:

• Experience with RISC-V, ARM, and/or MIPS CPU 
• Experience with multi-core and coherency 
• Familiarity with functional safety flows and requirements 

Here’s what you can expect from us: 

At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers. 

At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave! 

More about us: 

MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products. 

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.