Search the 21 jobs at MIPS

The Staff/Senior Staff Engineer will be responsible for pre-silicon functional verification of the Coherency Manager along with CPU, Subsystem, and Memory Hierarchy designs. The role involves designing verification environments, implementing best practices, and resolving performance issues before silicon production, leveraging expertise in CPU verification and cache coherency.

Lead a team developing bare-metal and RTOS software for RISC-V CPUs. Responsibilities include designing CPU firmware, developing RTOS ports, optimizing software with hardware, mentoring team members, and interacting with cross-functional teams on project planning and progress tracking.

The Sr. Staff/Lead Engineer will lead a team in the development of Linux software for RISC-V CPUs/Platforms, mentor team members, design and implement software solutions, and contribute to the open-source ecosystem. Responsibilities include code review, optimizing software for hardware platforms, and ensuring documentation is maintained.

The Sr. Staff Design Engineer leads RTL development and integration for high-performance SoCs, focusing on micro-architecture, design features, verification support, and collaboration with a multi-functional engineering team. Responsibilities include ensuring design performance goals in terms of power, area, and timing.

The Sr. CPU Verification Engineer will lead CPU verification using functional and formal methodologies, ensuring verification closure for CPU designs. Responsibilities include creating functional test plans, working with cross-functional teams, and applying knowledge of CPU architectures and verification tools.

The Sr Staff Trace Design Engineer will lead RTL development for Trace micro-architectural design, writing specifications, and refining designs for performance, power, and area. Responsibilities include functional verification support and collaborating with engineering teams on physical design aspects such as timing and reliability.

The Senior Staff Verification Engineer will lead verification efforts for CPU designs, develop functional test plans, and analyze coverage while working closely with designers across multiple sites. The role includes hands-on experience with various programming languages and tools for SOC verification, and demands strong problem-solving skills.

The MMU Design Engineer will design and implement MMU architectures for RISC-V CPUs, optimizing memory access and management, collaborating with CPU design teams, preparing documentation, and staying updated on industry trends.

The role involves leading the RTL development of a high-performance Floating-Point Unit, focusing on microarchitecture design, functional verification, and collaborating with multi-functional teams to meet performance and power targets.

The Embedded Software Engineer will design and implement software for RISC-V platforms, focusing on tasks such as developing CPU firmware, RTOS ports, performance benchmarks, and collaborating with hardware and architecture teams. The role involves using emulators, analyzing software performance, and supporting customer onboarding and troubleshooting.

In this role, you will design and implement embedded software for RISC-V CPUs and platforms. Responsibilities include Linux kernel support, device driver development, creating customized Linux distributions, and contributing to open-source projects. Additionally, you'll analyze and optimize software using hardware and emulators and collaborate with architecture and hardware teams to enhance CPU cores.

The Design Implementation Lead will oversee backend implementation of RISC-V cores, focusing on PPA optimization. Responsibilities include conducting synthesis, maintaining design methodology, and mentoring junior members while ensuring design validation and power analysis.

The Design Implementation Engineer is responsible for the backend implementation of RISC-V cores, overseeing synthesis, place and route, and timing closure. They will collaborate with RTL designers to ensure design closure and address any design gaps, while also focusing on power, performance, and area optimization.

The CPU Verification Engineer will develop and implement functional test plans for complex CPU IP, analyze coverage, debug issues, and enhance verification methodologies while collaborating closely with design teams. The role focuses on utilizing scripting and various verification tools, requiring strong analytical skills and a knowledge of CPU architectures.

In this role, you will have technical ownership of automating software development processes, focusing on building, testing, and deploying containers. You'll collaborate with teams to enhance software quality, implement security measures, and maintain application reliability for SaaS products.

The Staff Engineer - Full Stack Developer will lead the development and implementation of a cloud application for the semiconductor industry, focusing on product configuration and customer support. Responsibilities include managing the entire software development process, designing front-end and back-end services, writing APIs, and ensuring application performance and security.

The Sr Staff Trace Design Engineer will lead RTL development for TraceUnit design, specifying micro-architecture, and optimizing for power, performance, and area. The role includes collaborating with cross-functional teams for design validation and integrating functional verification support, ideally requiring significant experience in SOC and Trace architectures.

The MMU Design Engineer will design and implement MMU architectures for RISC-V CPUs, focusing on performance and scalability. Responsibilities include collaborating with teams for integration, creating documentation, and researching memory management techniques.

The Senior Design Verification Engineer will lead verification efforts for CPU designs, collaborating with designers and architects. Responsibilities include developing functional test plans, writing directed tests in C and SystemVerilog, analyzing coverage, and enhancing the verification environment utilizing various verification tools and methodologies.

The role involves leading RTL development of a high-performance Floating-Point Unit (FPU), focusing on architecture, design features, performance, power, area, and functional verification. The engineer will collaborate with teams to validate designs and optimize features across multiple execution modes.