Software Engineer — SmartHLS Applications (FPGA/SoC)

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Job Description:

Role Summary
Design, productize, and support SmartHLS-based C++ open-source libraries and reference applications for Microchip’s PolarFire® FPGA and PolarFire® SoC families. This role blends hands-on feature development, on-board test/CI bring-up, developer-experience tooling, and Field Application Engineer and customer training. You will collaborate with the HLS compiler team, Continuous Integration/SQA, and FAE teams to deliver high-quality, well-documented IP and examples that accelerate customer adoption.

About the Team
The SmartHLS Applications team builds reusable C++ libraries (e.g., Vision, DSP, Math, etc.) and for example designs, integrates them with Libero® SoC, and maintains on-board/CI testing to ensure reliability across supported boards (e.g., BeagleV-Fire, Icicle, PolarFire Video Kit, Discovery Kit, …). The team also authors hands-on labs and training materials for FAEs and customers.

Key Responsibilities
• Build and maintain SmartHLS C++ libraries and examples
• Own feature development and PRs in internal GitHub repositories
• Deliver production-quality HLS IP, including verification, QoR analysis, and demo integration.
• Develop and deliver FAE/customer training (labs, docs, IDE walk-throughs), including Embedded SW, HLS, and System-level flows.
• Stand up and improve on-board/CI testing for SmartHLS (for Windows and Linux); triage failures and drive fixes with CI owners.
• Operate and enhance a board-farm manager to reduce board contention and improve reservation/health checks of the hardware boards.
• Support cross-team handoffs by aligning deliverables and follow-ups with internal and external customers.

Requirements/Qualifications:

Minimum Qualifications
• Bachelor’s or Master’s degree in Computer Science, Software Engineering, or related fiel
• Strong modern C/C++ and Python programming skills.
• Working knowledge of FPGA/SoC design flows.
• Experience authoring training and developer guides (e.g. step-by-step labs & documentation).
• Hands-on with FPGA development boards.
• Git/GitHub development with PR workflows for internal/external repositories.

Preferred Qualifications
• Familiarity with RISC-V is a plus.
• Experience using Generative AI tools and frameworks such as LLMs & RAGs.
• Familiarity with High-Level Synthesis.

Tools & Technologies You’ll Use
• Libero® SoC 2025.1, SmartHLS,
• C/C++, Python, GenAI frameworks
• Jenkins, Confluence, Jira, Bitbucket and GitHub
• Linux and Windows development environments
• RISC-V (Soft Mi-V) reference platforms and evaluation boards

Work Model
Hybrid — Primary work location is Toronto, Ontario. The team collaborates in person for select planning, workshops, or lab activities; remote work is supported for focused development.

Travel Time:

0% - 25%

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position is $90,000 - $140,000.*

Ontario Accommodation:

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