Senior RTL Design Engineer - Front-End / Back-End SD (SoC/SSD)

Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up. In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas. Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to be the #1 NAND memory company in the world. At Solidigm, we view problems as opportunities to define innovative solutions that hold the power to change the world and unleash the potential technological needs that the future holds. At Solidigm, we are One Team that fosters a diverse, equitable, and inclusive culture that embraces individual uniqueness and empowers us to bring our best selves to deliver excellence in support of Solidigm's vision and mission to be the go-to partner for optimized data storage solutions. You can be part of the takeoff of an innovative business that develops cutting-edge products, delivers strong business value for customers, provides an engaging workplace for its employees, and serves a greater impact on the world. This is a golden opportunity for the right applicant to join us and help design, build, and lead Solidigm. We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization. We are seeking applicants who will grow and thrive in our culture; be customer inspired, trusting, innovative, team-oriented, inclusive, results driven, collaborative, passionate, and flexible.

We are looking for an experienced Senior RTL Design Engineer with deep expertise in front-end and/or back-end digital logic design to help drive the development of next-generation SoC/SSD architectures. This role involves architecture definition, RTL design, synthesis, timing closure, and design verification support for complex digital subsystems. The ideal candidate will have a strong background in digital design, RTL development, and backend integration, particularly in storage or memory-related applications.

In this role, you will be tasked to drive these 2 primary FE/BE objectives of Logic design:

Front-End:

• Help define logic HW / FW controller architecture for 3D NAND design. This involves deep-understanding of existing controller design and advancing its architecture for best die-size and power consumption. RTL design is in System Verilog and custom FW primarily in basic assembly language. You'll also be tasked to verify all timing closure of the designated blocks

Back-End:

• Help execute the advanced RTL-to-GDS process of the several large logic controller partitions of 3D NAND chip design. This involves synthesis, place-and-route, timing closure, post-r2g to schematic conversion on Virtuoso, and layout DRC. You'll also help drive the flow improvement from the existing DC/ICC2 flow to the more advanced Fusion Compiler flow

• MS with 7+ years or BS with 10+ years of experience in FE/BE design
• Expert knowledge of System-Verilog, Mem Controller architecture
• Expert in Synthesis, Place & Route, PrimeTime, and DRC
• Expert in DC/ICC2 and Fusion-Compiler tool set/env
• Strong knowledge of design PDK esp. stdcell
• Strong background in physical layout design and layout verification
• Solid Virtuoso schematic/layout environment

The compensation range for this role is $139,480 - $209,760. Actual compensation is influenced by a variety of factors including but not limited to skills, experience, qualifications, and geographic location. 

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