As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
The Role
As a Cache Subsystem Microarchitect and RTL design engineer at SiFive you will be part of a team of engineers who are passionate about designing industry-leading CPU cores and cache subsystems, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
Responsibilities:
You will architect, design and implement new high performance cache subsystems in SiFive's RISC-V CPU core generators and enhance features and performance in existing ones.
Work on the microarchitecture development and specification; ensuring that knowledge is shared via great documentation and participation in a collaborative design culture.
Perform initial sandbox verification and work closely with the verification team to create and execute detailed verification test plans.
Work with the physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
Collaborate with the performance modelling team for performance exploration and optimization to meet performance goals.
You will have:
At least three years of relevant industry experience working on high-performance, energy-efficient cache subsystem designs, ideally within a CPU or GPU subsystem.
A background of successful cache subsystem development from architecture through to tapeout.
Expertise in multi-level coherent cache architectures and designs.
Experience with TileLink or other similar interconnect architecture.
Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL.
Attention to detail and a focus on high-quality design.
Ability to work well with others and a belief that engineering is a team sport.
A Bachelor's or Master's degree in EE, CE, CS or a related technical discipline, or equivalent experience.
Nice to have:
Knowledge of RISC-V architecture.
Experience with Scala and/or Chisel.
Understanding of IP verification tools and methodologies such as UVM and Formal.
Knowledge of at least one object-oriented and/or functional programming language.
If you want to do incredible work and be challenged by exciting, truly innovative projects that will test the boundaries of your skills and creativity, then SiFive is the place for you! Be proud of your work. Do things better. Join SiFive
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
TaiwanAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Skills Required
- At least three years of relevant industry experience
- Expertise in multi-level coherent cache architectures
- Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL
- A Bachelor's or Master's degree in EE, CE, CS or related discipline
What We Do
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
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