Senior Principal Engineer - Physical Design

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

This position is with ASIC design physical implementation (PD) team part of Custom Compute and Storage (CCS) business unit at Marvell, Bangalore. This team is a part of the global Implementation team that plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM’s, CSSP’s. We are looking for strong technical leaders in the domain of physical design having Full-Chip implementation experience on hierarchical designs using industry standard tools.

What You Can Expect

• Take on a Full Chip Lead/Technical Manager role, engaging with customers and stakeholders at a global level to drive technical deliverables and manage dependencies across the design cycle, including DFT, Timing, Front-End (FE), and Power.
• Manage multi-million-gate hierarchical designs, including tasks like sizing, partitioning, chip top clock tree planning, and IO and bump planning. Ensure successful sign-offs for EM/IR, crosstalk, and DFM checks.
• Work on cutting-edge designs using the latest technology nodes (5nm, 3nm, 2nm), collaborating with global teams and demonstrating excellent problem-solving skills.
• Provide technical guidance, review designs, and mentor junior engineers, fostering a collaborative and productive environment.
• Utilize your proficiency in scripting languages such as PERL, TCL, AWK, or Shell to optimize workflows. Excellent written and oral communication skills are essential for effective collaboration and documentation.
• This role is ideal for individuals with strong technical expertise, problem-solving skills, and a passion for leading complex design projects in a global, cutting-edge environment.

What We're Looking For

• Have completed a Bachelor’s OR a Master's Degree in Electronics/Electrical/VLSI field and have atleast 18+ years of related professional experience in physical design at Partition/Subsystem/Chip level with a proven track record of successful tape-outs.
• Proficiency in RTL to GDS flows and methodologies, with significant experience in advanced nodes (7nm, 5nm, or below).
• Working knowledge of scripting languages (Perl, TCL, AWK, Python).
• Familiarity with Verilog/VHDL is advantageous.
• Strong interpersonal skills and the ability to work effectively in a collaborative team environment.
• In-depth expertise with industry-standard tools for synthesis, floor planning, placement, clock tree synthesis, routing, and physical verification
• Exceptional verbal and written communication skills

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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