Senior Physical Design Engineer

Job Details:

Job Description: 

Employees of the Central Engineering Group (CEG) have an exciting opportunity before them: To grow Intel's leadership position in the rapidly evolving market by delivering the best silicon, software and services that meet a wide range of customer requirements. The group, a fresh, dynamic collaboration between Intel's Business Units, uses assets from across all of Intel. The CEG team is dedicated to helping Intel drive the next major growth inflection through productivity and new business models that are emerging as a result of IoT, AI, Edge and Networking applications. The Go To Market (GTM) team is looking for driven Engineers to take part in the development of products tailored to Intel's growing new business initiatives. If you are as excited as we are about these new emerging trends in technology, you are welcome to apply to this position.

The primary responsibilities for this role will include, but are not limited to:

• Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
• Conducting all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Running verification and signoff flows, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design review.
• Analyzing results and recommending improvements for current and future product architectures.
• Using your unique expertise in aspects of structural and physical design to help others, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT.
• Optimizing our designs to improve product level parameters such as power, frequency, and area.
• Participating in the development and improvement of physical design methodologies and flow automation.

A successful candidate will have proven experience demonstrating the following skills and behavioral traits:

• The ideal candidate should have the ability to communicate well with counterparts and key stakeholders including cross-site partners.

Qualifications:

Minimum Qualifications:

Minimum qualifications are required to be initially considered for this position.

• Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering, or equivalent.
• At least 3 years of experience in running Synthesis, Place and Route physical design tools and flows and sign-off.
• At least 3 years of experience in Unix/Linux and shell programming.
• Advanced English level.
• Costa Rican unrestricted work permit.

Preferred Qualifications:

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• 3 years of experience in writing and producing software code using languages such as PERL, TCL, and PYTHON.
• Proven experience in use of AI tools on technical contexts in engineering.

          

Job Type:Experienced Hire

Shift:Shift 1 (Costa Rica)

Primary Location: Costa Rica, San Jose

Additional Locations:

Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.