Job Description
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below.
Life at Intel
To support Intel Foundry strategy, we are looking for talents to join this exciting journey to drive design enablement in quality and reliability area on Intel leading technology nodes to build industry competitive design platform supporting customer design on Intel Si and package technologies. The general reliability design enablement includes PDK (Process Design Kits), TFM (tool/flow/methodology), Foundational IP (library, memory, analog IP) and DFR (Design for Reliability) to achieve best PPA (Power Performance Area) and reliability co-optimization.
This role will be responsible for but not limited to:
- Definition and generation of reliability related PDK design rule and collateral covering all reliability mechanism, QA (quality assurance) and benchmarking analysis.
- Drive industry EDA (Electronic Design Automation) tool and flow enablement in synergy with PDK development, work with internal partners and EDA vendors to deliver competitive TFM to support design reliability verification.
- Competitive analysis and benchmarking technology reliability, plan and deliver industry leading PDK, design rule, design collateral, TFM and IP ecosystem to enable internal and external customer design on Intel technology.
The Candidate Should Exhibit the Following Behavioral Traits:
- Excellent written and verbal communication and presentation skills.
- Passion for quality and attention for details and procedures, looking for opportunities to drive efficiency and innovations.
- Demonstrated capability to drive quality enhancements projects.
- Strong team player with proven ability to work in diverse multi-cultural environment.
- Must be flexible and adaptable to ensure program commitments are met on time in a dynamic work environment.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
What we need to see (Minimum Qualifications):
- Bachelor's degree in electrical engineering, physics or a related field and 6+ years of relevant work experience or 4+ years of relevant experience and a master's degree, or a PhD degree with 2+ years of relevant experience.
- 3+ years' experience in one of the following areas: PDK development, reliability tool and flow, design for reliability, Circuit, IP and SOC design reliability validation using PDK, EDA tool and flow development.
Preferred Qualifications:
- Master's degree in electrical engineering, physics, or related field, or Ph.D. degree in electrical engineering, physics, or related fields.
- Hands-on Experience on PDK development and validation; knowledge and understanding of PDK fundamentals; reliability design rules and their implementation in PDK and TFM.
- Capability to use AI or program skills to write code, agent or script for design rule, techfile generation and quality assurance.
- Experience on PDK, EDA tool/flow development, design flow application and interaction with IP and SOC design validation and sign-off; design impact and risk assessment in related reliability area.
- Experience and knowledge on reliability verification and physics, such as aging including BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection), Electro-Migration, high voltage design, EOS (Electrical Over-Stress), ESD (Electrostatic Discharge).
- Experiences and skills in program management, stakeholder management, and strong communication skills.
Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.
Amazing Benefits!
Here at Intel, we invest in our people. Beyond health, dental, and retirement benefits, Intel’s benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment. Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. Find more information about our Amazing Benefits here: https://jobs.intel.com/benefits
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Folsom, US, California, Santa ClaraPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $173,660.00-245,160.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's degree in electrical engineering, physics, or a related field with 6+ years of relevant experience
- Master's degree with 4+ years of relevant experience, or PhD with 2+ years of relevant experience
- 3+ years of experience in PDK development, reliability tools and flows, design for reliability, circuit/IP/SoC reliability validation, or EDA tool and flow development
- Master's or PhD degree in electrical engineering, physics, or a related field
- Hands-on experience with PDK development and validation, PDK fundamentals, reliability design rules, and their implementation in PDK and TFM
- Ability to use AI or programming skills to write code, agents, or scripts for design rule and techfile generation and quality assurance
- Experience with PDK, EDA tool/flow development, design flow application, IP and SoC validation/sign-off, and reliability risk assessment
- Knowledge of reliability verification and physics, including BTI, HCI, electromigration, high-voltage design, EOS, and ESD
- Experience and skills in program management, stakeholder management, and communication
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
Intel Insights
What We Do
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.
