Senior ARM RTL Design - Architect

Posted 16 Hours Ago
Be an Early Applicant
Austin, TX
Senior level
Cloud • Hardware • Software • Semiconductor
The Role
The Senior RTL Design Architect at Cadence will be responsible for CPU and interface IP selection, digital design, creating detailed micro-architecture specifications, and collaborating with verification teams. The role emphasizes RTL development and physical design deliverables, ensuring timely IP delivery while working with multidisciplinary teams.
Summary Generated by Built In

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Solutions (North America) team is looking for an experienced RTL designer to contribute to architecture and design for next generation SoCs targeting Hyper-Scalar, Automotive, IoT and Mil-Aero markets.

Position presents a learning and growth opportunity for candidate to develop into an architect (System) in the future.

Responsibilities:

  • CPU IP selection/configuration/integration for ARM and/or RISCV CPU and System IP
  • Design IP selection/configuration/integration for Memory and/or Interface IP (PCIe, Ethernet, USB and other)
  • Digital design and IP creation/ownership from High Level Arch Specification
  • Create detailed Micro-architecture specification, work closely with the architect
  • Understanding of performance measurement and refinement. Ability to work with verification/validation team to create performance verification plan
  • RTL development
  • Support Verification teams. Support test bench development, review verification and vPlans. Provide timely specification clarifications and debug support
  • Physical design deliverables. Create functional timing constraints, synthesize RTL to ensure power and area targets are met and constraints are correct
  • Plan development schedule in detail and track deliverables to ensure timely IP delivery to all consumers
  • Work with multi-disciplinary teams to ensure design block/IP success for all target specifications in Silicon

Qualifications: 

10+ years of Front End design and/or verification.with a BS/MS Engineering or Computer Sciences

Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration

Expert in RTL design (Verilog), simulators debuggers

Hands on Experience in Synthesis, SDC creation and support PD and STA teams.

Hands on experience on CDC/RDC setup, cleanup and ownership.

Experience in C/C++ and/or Python (or scripting language)

Experience in driving results in multi-disciplinary organization

Desirable:

A Self-motivated person with good communication and design management skills

Experience with Cadence front end toolset

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We’re doing work that matters. Help us solve what others can’t.

Top Skills

C
C++
Python
Verilog
The Company
HQ: San Jose, CA
8,216 Employees
On-site Workplace
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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