Senior Memory Design Engineer

Posted Yesterday
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Electronics City, Bangalore, Karnataka
Senior level
Semiconductor
The Role
The Senior Memory Design Engineer will lead the design and development of SRAM memory compilers and perform circuit design/simulation, statistical analysis, and timing analysis. Responsibilities include design tuning and performance sign-off to meet yield targets, as well as conducting signal and power integrity analysis.
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Job Description:

JD for Senior Design Engineer

1) Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies
2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
3) Development of critical path and characterization flow to perform detailed margin and characterization simulations.
4) Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off
5) Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
6) Logic simulations and detailed timing analysis of key paths in high speed memory design.
7) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design. 

Skill Sets/Prerequisites 

1) Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits
2) Experience in Designing and driving one or many Memory Compilers Specifications to final release 
3) Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design
4) Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.
5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools
6) Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc
7) Experience in Skill/Perl/Python Scripting is a strong plus 
8) Experience in Understanding the layout design issues in sub nanometer regime is a must. 
9. Expertise in Understanding Memory DFT is a Plus.
10. Masters Degree with 4+ Years or Bachelors Degree with 5+ years

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Top Skills

Cmos
The Company
HQ: San Jose, CA
38,985 Employees
On-site Workplace
Year Founded: 1991

What We Do

Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs,
develops and supplies semiconductor and infrastructure software solutions.

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