Senior Manager, Design Verification Engineering

Posted 13 Days Ago
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Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Artificial Intelligence • Hardware • Automation • Manufacturing
The Role
Lead and mentor a large DV team to define and execute verification strategies for complex digital IP and subsystems. Drive test plans, coverage closure, mixed-signal and gate-level verification, liaise with design, architecture and firmware teams, and improve DV methodologies across product lifecycle.
Summary Generated by Built In

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

          

Senior Manager, Design Verification
The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Digital Systems IP team within the Engineering Enablement organization. The IP team builds, curates and guides the development of IP across ADI. 

We’re seeking a highly experienced, seasoned DV expert with experience in leading DV efforts for verification of different IP components and subsystems from scratch.

About the role
In this position the successful candidate will lead and be exposed to the entire product lifecycle from concept phase, through design, verification, implementation, and release of IP to various product teams. They will collaborate with the wider ADI technical community, which affords an opportunity to work with many business units in ADI with exposure to many technologies and products. This is a senior role with the opportunity to create real impact within the organization and build a promising career. 
 

Responsibilities

  • Verification of complex Digital designs and sub-systems using leading edge verification methodologies.
  • Manage and mentor a high performing team of DV engineers, plan the DV strategy, manage the execution
  • Defining verification strategy, test plans, tests and verification methodology for chip-level verification.
  • Interact with various BU teams that use or explore ADIP IP. Understand the SoC use cases and enhance DV to support them
  • Working with the design team in generating test-plans and closure of code and functional coverage
  • Continuous interaction with Design, Architecture and Firmware teams
  • Tracking and management of design verification improvements
     

Required Qualifications

  • Bachelor’s or Master’s degree in Electronic Engineering or a related field, with at least 15 years of ASIC design verification experience.
  • Experience managing teams of 20 or more people.
  • Strong leadership skills with the ability to define and execute verification strategies.
  • Proven ability to communicate effectively with peers, managers, and project stakeholders in both written and verbal formats.
  • Broad expertise in digital verification, including constrained-random verification, functional and code coverage, assertion-based methodology, formal verification, analog behavioral modeling, SystemVerilog real-number modeling, behavioral model validation, and mixed-signal simulators such as Cadence Xcelium.
  • Experience applying AI tools to design verification workflows.
  • Experience with processor-based verification and gate-level simulation flows for SoC verification.
  • Proficiency in Verilog, C/C++, SystemC, Java, TCL, Perl, Python, and shell scripting.
  • Experience with Property Specification Language (PSL), MATLAB, including co-simulation and HDL generation, and digital signal processing is a plus.
  • Experience with low-power methodologies such as CPF and UPF is a plus.
  • Excellent interpersonal and communication skills, with enthusiasm for taking on diverse challenges.
  • Self-motivated and enthusiastic.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

          

Required Travel: Yes, 10% of the time

          

Shift Type: 1st Shift/Days

Skills Required

  • Bachelor's or Master's degree in Electronic Engineering or related field
  • At least 15 years of ASIC design verification experience
  • Experience managing teams of 20 or more people
  • Ability to define and execute verification strategies and lead teams
  • Broad expertise in digital verification: constrained-random, functional and code coverage, assertion-based methodology, formal verification
  • Experience with mixed-signal verification, analog behavioral modeling, SystemVerilog real-number modeling, and mixed-signal simulators (e.g., Cadence Xcelium)
  • Experience applying AI tools to design verification workflows
  • Experience with processor-based verification and gate-level simulation flows for SoC verification
  • Proficiency in Verilog, C, C++, SystemC, Java, Tcl, Perl, Python, and shell scripting
  • Proven written and verbal communication skills and ability to interact with stakeholders
  • Experience with Property Specification Language (PSL), MATLAB, co-simulation, HDL generation, and digital signal processing
  • Experience with low-power methodologies such as CPF and UPF
  • Self-motivated, enthusiastic, and able to tackle diverse challenges

Analog Devices Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Analog Devices and has not been reviewed or approved by Analog Devices.

  • Retirement Support The 401(k) program is described as a standout feature, with company contribution up to 8% of base salary and immediate vesting. This structure strengthens long-term value even when cash compensation perceptions vary.
  • Healthcare Strength Health coverage is positioned as comprehensive, including medical, dental, and vision options along with disability and life insurance. Day-one eligibility and multiple plan choices add to perceived robustness.
  • Leave & Time Off Breadth Paid time off appears broad, with vacation ranging from roughly 17–25 days and increasing up to five weeks with tenure, alongside sick time and paid holidays. Parental leave and related time-off provisions further expand coverage.

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The Company
HQ: Wilmington, MA
20,292 Employees
Year Founded: 1965

What We Do

Analog Devices, Inc. (NASDAQ: ADI) operates at the center of the modern digital economy, converting real-world phenomena into actionable insight with its comprehensive suite of analog and mixed signal, power management, radio frequency (RF), and digital and sensor technologies. ADI serves 125,000 customers worldwide with more than 75,000 products in the industrial, communications, automotive, and consumer markets. ADI is headquartered in Wilmington, MA.

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