Senior FPGA & Firmware Engineer - SDR

As a Senior member of the Mesh & Opportunistic Networking team, you will own the FPGA realization of the digital signal processing that powers our software-defined radio. You will take wireless communication algorithms from concept through behavioral modeling in MATLAB/Simulink, into synthesizable RTL, and onto silicon — meeting aggressive timing, resource, and power targets on a Zynq UltraScale+ MPSoC. You will apply deep expertise in DSP, digital communications, and FPGA design to deliver a robust, high-performance OFDM modem, and you will collaborate closely with firmware, systems, RF, and product engineering to bring the full radio together. You will mentor junior engineers, raise the technical bar for our model-based design and verification practices, and continue to grow your own technical leadership. Join a passionate engineering team dedicated to overcoming complex challenges, and help deliver technologies that positively impact Law Enforcement, Public Safety, and their surrounding communities.

Location - This role is based out of our Boston or Scottsdale offices and follows a hybrid schedule. We rely on in-person collaboration and ask that team members work onsite Tuesdays through Fridays, with the flexibility to work remotely on Mondays, unless there is an approved workplace accommodation. We believe that connection fuels innovation, and our in-office culture is designed to foster meaningful teamwork, mentorship, and shared success.

• Research, model, and implement industry-leading SDR and digital communications algorithms — OFDM modulation/demodulation, FFT/IFFT, channel estimation and equalization, synchronization, MIMO, and forward error correction (LDPC) — for products in our mesh and connected-device portfolio
• Develop floating- and fixed-point behavioral reference models in MATLAB/Simulink, make quantization and architecture trade-offs, and validate algorithm performance against link-budget and BER/PER requirements
• Generate and integrate RTL from Simulink using HDL Coder, and author hand-written VHDL/Verilog where custom or performance-critical logic is required
• Implement designs in Vivado through the full flow — synthesis, place-and-route, and timing closure — authoring and refining XDC timing and physical constraints to meet timing on high-utilization, multi-clock designs
• Architect and implement on-chip interfaces and data movement: AXI4 / AXI4-Stream, DMA, register interfaces, FIFOs, and robust clock-domain-crossing (CDC) logic
• Build and maintain rigorous verification: Simulink/HDL co-simulation, bit-true comparison against the reference model, RTL testbenches, and automated regression suites
• Integrate the modem with the RF transceiver front end (e.g., ADRV9001) and with the ARM application cores, partitioning functionality across the heterogeneous SoC
• Collaborate with electrical engineering on concerns that span the FPGA/RF boundary — power and thermal budgets, generation of test and characterization waveforms, and digital pre-distortion (DPD) for power amplifier linearization
• Bring up, characterize, and debug the radio on hardware using oscilloscopes, logic/protocol analyzers, spectrum and vector signal analyzers, and on-chip debug (ILA/VIO)
• Collaborate with firmware engineering to define and debug the hardware/software interface, register maps, and data pipelines
• Evaluate and document design outcomes, timing/resource reports, and verification results, and present findings to the design team for review and further action
• Optimize performance, area, and power through micro-architecture refinement, pipelining, and resource sharing, guided by simulation and hardware measurement
• Develop and maintain design documentation, interface control documents, and release artifacts needed for product integration
• Mentor junior engineers and contribute to team knowledge sharing and best practices in model-based design and FPGA development

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a similar engineering discipline
• 6+ years of industry FPGA/RTL design experience taking digital logic from architecture through synthesis, timing closure, and hardware bring-up
• Highly proficient in RTL design with VHDL and/or Verilog/SystemVerilog, including synthesizable coding practices and design for testability
• Strong hands-on proficiency with the Xilinx/AMD Vivado toolchain — synthesis, implementation, timing constraints (XDC), and timing closure on complex, high-utilization designs
• Demonstrated experience with MATLAB and Simulink for algorithm modeling, and with model-based design workflows
• Solid foundation in digital signal processing and digital communications: sampling, filtering, FFTs, modulation/demodulation, and an understanding of wireless link fundamentals
• Experience with fixed-point arithmetic, quantization analysis, and the trade-offs between numerical precision, area, and performance
• Proficient with on-chip interconnect and interfaces — AXI4/AXI4-Stream, DMA, memory interfaces — and with clock-domain-crossing design
• Strong RTL verification skills: testbench development, HDL simulation, and verifying RTL against a golden/reference model
• Strong hands-on proficiency with FPGA and system bring-up and debug using laboratory tools: oscilloscope, logic/protocol analyzers, spectrum/signal analyzers, and integrated logic analyzers (ILA/VIO)
• Proficient with modern AI-assisted development tools and coding assistants (e.g., Claude Code, Cursor, GitHub Copilot), and able to apply them effectively and responsibly to accelerate design, verification, scripting, documentation, and debug
• Independent contributor capable of developing complex designs within cross-functional and geographically diverse engineering teams
• Strong proficiency in documentation, analysis, and presentation tools, including Word, Excel, and PowerPoint

• Master’s or PhD in Electrical Engineering, Communications, or Signal Processing
• Production experience with HDL Coder (or equivalent high-level synthesis / model-to-RTL) workflows, including code generation, optimization, and verification of generated RTL
• Hands-on experience implementing OFDM modems and/or channel coding (LDPC, Turbo, convolutional/Viterbi), MIMO, channel estimation, and synchronization in hardware
• Experience designing on Zynq / Zynq UltraScale+ MPSoC or other heterogeneous SoC/FPGA platforms, including hardware/software partitioning with embedded processors
• Experience integrating wideband RF transceivers (e.g., Analog Devices ADRV9001/ADRV9002) or other SDR front ends, and implementing or supporting RF impairment correction such as digital pre-distortion (DPD)
• Familiarity with software-defined radio platforms and frameworks (e.g., GNU Radio) and over-the-air testing
• Experience with version control (Git) and CI for HDL/model-based design
• Experience applying AI coding assistants to FPGA/HDL workflows — RTL generation and review, testbench creation, constraint and timing analysis, MATLAB/Simulink and Tcl scripting, and design documentation — with sound judgment about where generated output must be verified

• Competitive salary and 401k with employer match
• Discretionary paid time off
• Paid parental leave for all
• Medical, Dental, Vision plans
• Fitness Programs
• Emotional & Mental Wellness support
• Learning & Development programs
• And yes, we have snacks in our offices