Senior FPGA Engineer (Verilog/Alveo U45N)

Waypoint Trading Solutions is the infrastructure backbone of global trading. We provide secure, ultra-high-performance solutions, including sub-microsecond trading connectivity (Xpress), the world’s largest financial extranet (Radianz), and fully managed market data operations (Sentinel). Our platforms deliver nanosecond-level performance to 180+ global exchanges across 70+ countries.

We are developing next-generation monitoring and acceleration solutions for our high-speed, low-latency trading networks using advanced FPGA technology, with a primary focus on the AMD Alveo U45N platform.

As a Senior FPGA Engineer, you will lead the architecture, design, development, and optimization of sophisticated FPGA-based solutions that monitor and accelerate our mission-critical, ultra-low-latency trading infrastructure. You will drive complex network monitoring, high-performance packet processing, and custom datapath architectures that deliver deterministic reliability and performance in the most demanding financial markets environments. This is a senior, hands-on role focused on real-time, line-rate networking on AMD FPGA hardware within a Linux ecosystem.

• Architect, develop, and implement complex custom FPGA designs on the AMD Alveo U45N using the Vivado Design Suite, setting the technical direction for high-impact projects.
• Lead the design and optimization of high-speed network monitoring, packet capture, filtering, deep inspection, and analysis solutions for production low-latency trading networks.
• Design, integrate, and optimize advanced network interfaces, including Ethernet MACs, PCS/PMA layers, and custom protocols, to achieve sustained 100G+ line-rate performance with minimal latency.
• Drive OpenNIC-based FPGA NIC initiatives, including shell/role architecture, customization, QDMA integration, driver development, and full system-level optimization.
• Collaborate closely with network, systems, and trading infrastructure teams to deliver sophisticated monitoring capabilities that provide deep visibility into ultra-low-latency paths without introducing jitter or overhead.
• Own timing closure, including rigorous simulation, synthesis, implementation, and advanced debugging of complex FPGA designs.
• Profile, analyze, and continuously optimize designs for the lowest possible latency and highest throughput in live production trading environments.
• Mentor junior FPGA engineers, contribute to and maintain internal IP libraries, establish best practices, and support deployment, troubleshooting, and performance tuning in global data center environments.
• Document architectures and designs to a high standard while driving knowledge sharing across the team.

• Extensive experience with AMD/Xilinx FPGA development, with deep expertise in UltraScale+ architectures (Alveo U45N or equivalent high-end platforms).
• Strong proficiency with the full Vivado tool flow (synthesis, implementation, timing analysis, constraints, and simulation using Vivado Simulator or ModelSim/Questa).
• Expert-level understanding of networking protocols and low-level packet processing, including Ethernet, TCP/IP, UDP, PTP, and related high-performance techniques.
• Proven track record of designing and implementing high-performance network interfaces on FPGAs (Ethernet MACs, DMA engines, transceivers, etc.).
• Hands-on, production-level experience with OpenNIC or similar open-source FPGA NIC frameworks, including shell/role development, QDMA, driver integration, and system-level customization.
• Highly skilled in Verilog/SystemVerilog, with a strong emphasis on high-frequency, deeply pipelined, resource-efficient designs.
• Solid experience working in Linux environments, including kernel drivers, user-space applications, and scripting for deployment and automation.
• Deep familiarity with high-speed interfaces: SFP+/SFP28/QSFP (10/25/40/50/100G Ethernet), PCIe Gen3/4, and high-speed transceivers.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field (or equivalent senior-level experience).