Senior FPGA Engineer, Networking & Security

Muon Space is seeking a Senior FPGA Engineer specialized in onboard networking, cryptography and security to design the network fabric and security architecture of our next-generation spacecraft, to join our High Performance Compute (HPC) team. You'll define how data moves across the spacecraft, from sensor front-ends through payload compute to downlink, and how it stays secure, both in flight and end-to-end to the ground.

This is a hands-on FPGA engineering role with strong architectural influence: you'll define the concepts, write the RTL, and work shoulder-to-shoulder with our Staff Architect, EE team, and payload engineers to bring your solutions to life.

This position is hybrid and requires working on-site in our San Jose, CA office three days per week.

• Define the onboard networking architecture for Muon spacecraft, including switching, routing, packet filtering, firewalling, deep packet inspection, and VPN concepts.
• Define and implement end-to-end encryption, packet-based encryption at router level, file-based encryption for onboard and downlink data.
• Drive the definition of an onboard Ethernet switching and routing device and evaluate implementation options (COTS, semi-custom, fully custom FPGA-based).
• Design and build a spacecraft NoC (Network-on-Chip) and robust FPGA-to-FPGA links, with continuous link health monitoring and reporting.
• Own the Ethernet PHY and MAC integration on FPGAs, link aggregation, and signal-integrity trade-offs, in close partnership with the HPC architecture and Electrical Engineering team.
• Apply FEC schemes (e.g., Reed-Solomon) to onboard and inter-FPGA links; translate networking and coding requirements into implementable RTL.
• Integrate the network fabric with customer payloads, ensuring interoperability and low-level link validation.
• Publish white papers on Muon's networking and security solutions and represent this work internally and (where appropriate) externally.
• Work hand-in-hand with the Staff Onboard Compute Architect on the team to harmonize networking and security into the broader compute architecture.

• Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field, plus 5+ years of professional FPGA engineering experience, with a specialization in networking, cryptography, security, or high-speed I/O.
• Deep, hands-on experience with Ethernet, link aggregation, and signal-integrity considerations, specifically at higher direct attached copper (DAC) lane rates.
• Strong practical experience applying cryptographic algorithms in hardware or firmware: AES, AES-GCM, ECC, IPSec/VPN handshakes, and familiarity with post-quantum cryptography (PQC).
• Working knowledge of FEC schemes, particularly Reed-Solomon, and the ability to translate BER and link-budget requirements into concrete FEC implementations.
• Proven experience defining network packet flows, switching/routing/filtering, deep packet inspection, firewalling, and VPN termination in embedded or FPGA-based systems.
• Strong HDL/RTL skills (SystemVerilog, Verilog, or VHDL) and familiarity with modern FPGA verification methodologies.
• Excellent written and verbal communication skills, including the ability to author white papers and architectural documents.
• Ability and willingness to obtain and maintain a U.S. security clearance. Active clearance is a plus.

• Experience with a variety of spacecraft networks including Ethernet and SpaceWire.
• Experience implementing or integrating NoC (network on chip) fabrics on FPGA.
• Familiarity with space-grade or rad-tolerant FPGA platforms.
• Prior work on spacecraft avionics, payload data handling, or secure space-to-ground links.
• Contributions to standards bodies, open-source cryptographic implementations, or published research.

The salary range for this role is $213,000 - $237,000, plus a competitive equity grant and comprehensive benefits package. Final compensation will be determined based on skills, qualifications, experience, and geographic location as assessed during the interview process.