Tech Lead Firmware Engineer (DDR technologies)

Posted 6 Hours Ago
Be an Early Applicant
Santa Clara, CA
Senior level
Big Data • Information Technology
The Role
The Tech Lead Firmware Engineer will design and develop Firmware to enable DDR technologies for innovative products at Astera Labs, focusing on CXL memory solutions. Responsibilities include debugging DDR-related issues and potentially collaborating with cross-functional teams on DDR memory interfaces.
Summary Generated by Built In

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com. 

Job Description:

As an Astera Labs Tech Lead Firmware Engineer, you will be designing and developing Firmware for enabling DDR technologies for future looking products defined by Astera Labs CXL memory solutions.

Basic qualifications:

  • Bachelor’s in Electrical engineering / Electronics / Computer Science or related fields.

Required experience:

  • 5+ years of experience in developing Firmware using C in Embedded environments.
  • Good knowledge in DDR Technology internals (DDR Training, DDR RAS, PMIC, RCD etc.)
  • Ability to debug DDR related issues.

Preferred experience:

  • Post-Silicon bring up and validation of DDR memory interfaces
  • Experience working with cross-functional teams and partners.
  • Pre-Silicon DDR bring up experience is a plus
  • Experience with RDIMMs, DDR controller/PHY tuning is a plus
  • Knowledge of Server memory performance and stability tuning for latency and bandwidth is a plus

The base salary range is 140,000.00 USD – 200,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Top Skills

C
The Company
HQ: Santa Clara, CA
148 Employees
On-site Workplace
Year Founded: 2017

What We Do

Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center.

Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning.

The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.

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