As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
The Role:
As a Senior Physical Design Engineer, you will be responsible for executing and optimizing the RTL-to-GDS implementation flow for our high-performance CPU cores. In this role, you will take ownership of block-level implementation and contribute to advanced design recipes to drive PPA (Power, Performance, Area) closure on leading-edge N3/N2 process nodes. This position focuses on high-quality technical execution, hands-on design closure, and utilizing automated, ML-enhanced methodologies to hit aggressive frequency and power targets within a highly collaborative team environment.
Key Responsibilities
Flow Execution & Validation: Implement, validate, and maintain production-ready RTL-to-GDS recipes using Synopsys Fusion Compiler based on established methodology guidelines.
Block Ownership: Take end-to-end implementation ownership of medium-sized CPU sub-blocks, driving them from RTL synthesis through to final GDS sign-off.
PPA Optimization: Drive block-level PPA closure and contribute to hierarchical closure efforts, utilizing advanced techniques in timing-driven placement, CTS, and routing.
ML Deployment: Hands-on utilization of ML optimization tools (such as DSO.ai) to perform design space exploration and achieve optimal PPA targets.
Technical Execution & Troubleshooting: Identify, debug, and resolve flow and tool-related issues at the block level, collaborating closely with the wider methodology and core engineering teams to bypass bottlenecks.
Cross-Functional Collaboration: Partner with IP teams (SRAM/Std Cell) and technical leads to analyze and model PPA impacts within your design blocks.
Automation & Scripting: Develop, enhance, and maintain robust Tcl/Python scripts to improve flow efficiency, ensuring repeatable and predictable results across design iterations.
Requirements
Experience: 4+ years of hands-on experience in Physical Design/Methodology, with a strong track record in digital implementation.
Node Knowledge: Solid experience with FinFET nodes (N5/N3); familiarity with N2/GAAFET challenges is a strong plus.
Tool Proficiency: Deep hands-on knowledge of the Synopsys digital implementation suite (Fusion Compiler, ICC2, PrimeTime, StarRC).
Design Understanding: Strong grasp of physical design concepts, including floorplanning, pin assignment, and timing budgeting within a hierarchical environment.
Automation Skills: High proficiency in Tcl and Python for flow customization, debugging, and data analysis.
Problem Solving: Proven ability to analyze and resolve complex timing, power, and congestion issues in high-speed, high-density blocks.
Teamwork: Excellent communication skills with a proven ability to collaborate effectively within a structured team environment and align with technical milestones.
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Skills Required
- 4+ years hands-on experience in Physical Design/Methodology and digital implementation
- Experience with FinFET nodes (N5, N3)
- Familiarity with N2 / GAAFET challenges
- Deep hands-on knowledge of Synopsys digital implementation suite (Fusion Compiler, ICC2, PrimeTime, StarRC)
- Strong grasp of physical design concepts: floorplanning, pin assignment, timing budgeting in hierarchical environments
- High proficiency in Tcl for flow customization and Python for scripting and data analysis
- Proven ability to analyze and resolve complex timing, power, and congestion issues in high-speed, high-density blocks
- Hands-on utilization of ML optimization tools for design space exploration (e.g., DSO.ai)
- Ability to take end-to-end block ownership from RTL synthesis through final GDS sign-off
- Excellent communication and teamwork skills to collaborate with methodology, IP, and core teams
What We Do
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
