The Role
Lead ASIC physical design activities including floor planning, power-grid planning, partitioning, placement, scan-chain reordering, clock-tree synthesis, routing, timing and signal-integrity closure, ECOs, physical verification, DRC, LVS, antenna checks, and IR-drop analysis. The role provides technical mentorship, coordinates with front-end ASIC teams, documents plans, and prioritizes project work.
Summary Generated by Built In
· He/She should be able to do block level / top-level floor planning, PG Planning, partitioning(for hierarchical designs), placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations. Should have worked on 45nm, 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
· Provide technical guidance, mentoring to physical design engineers.
· Interface with front-end ASIC teams to resolve issues.
· Excellent communication skills.
· Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
· Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.
· Expertise in scripting languages such as PERL, TCL.
· Strong Physical Verification skill set.
· Static Timing Analysis in Primetime or Primetime-SI.
· Good written and oral communication skills. Ability to clearly document plans.
· Ability to interface with different teams and prioritize work based on project needs.
Experience – 3 to 8 Years
Location: Hyderabad
Skills Required
- 3 to 8 years of experience in ASIC physical design
- Experience with 45nm, 28nm, or smaller process-node designs
- Experience with advanced low-power techniques, including voltage islands, power gating, and substrate bias
- Expertise in block-level and top-level floor planning, power-grid planning, hierarchical partitioning, placement, scan-chain reordering, clock-tree synthesis, routing, timing optimization, and ECOs
- Experience with timing analysis and closure, signal-integrity closure, extraction, and IR-drop analysis
- Strong physical verification skills, including DRC, LVS, antenna checks, and violation correction
- Extensive experience with Cadence, Synopsys, or Magma physical design tools
- Expertise in Perl and Tcl scripting
- Experience with PrimeTime or PrimeTime-SI for static timing analysis
- Ability to provide technical guidance and mentoring to physical design engineers
- Ability to interface with front-end ASIC and cross-functional teams
- Excellent written, oral, and communication skills
- Ability to clearly document plans and prioritize work based on project needs
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The Company
What We Do
Established in 1999, MosChip is the first fabless semiconductor company publicly traded in India with approximately 20 years of experience. MosChip is a semiconductor and system design company with a focus on turnkey ASICs, mixed signal IP and semiconductor, product engineering and IoT solutions catering to aerospace and defense, consumer electronics, automotive, medical and networking and telecommunications. Over the past two decades, MosChip has developed and shipped millions of ASIC connectivity ICs. MosChip’ s IoT solutions like smart lighting, smart metering and asset tracking are successfully deployed in volume.
