Senior Engineer II - Backend Implementation

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

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Job Description:

Implementation Engineer
The AES Implementation team is responsible for creating the design of a device by providing technical expertise through cutting edge design
tools and technology. This team works closely with various business unit product development teams to ensure the design is physically
realizable.
As a Design Implementation engineer, the candidate will be mentored by the team, be engaged into projects to perform the constraint development and timing closure to ensure the design is implemented correctly with various checks/verification/audit.

Also, be involved in design flow/methodology definition and development to ensure the design team is always using best-in-class design methodology.
Responsibilities:

• Perform constraint development, STA on complex digital integrated circuits at the block, subsystem or device level (100K to 20M+ gates) which are coded in VHDL/Verilog.
• Work with project leaders to meet timing closure, area, power, and performance requirements for macro/device under development.
• Good Understand Design-For-Test concepts and methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage, and generation).
• Develop Constraints, analysis and debugging for Func, BIST and DFT modes
• Full chip and block level timing closure for various stages of the entire design process (RTL, Synthesis, Place and Route and STA Signoff).
• Enhance and maintain all STA flows and methodology for multiple designs and across different technologies.
• Work on all aspects of timing closure including Design rule checks, constraint validation, Noise analysis etc.
• Work with various IP owners in developing and refining STA constraints for both full chip and block level.
• Low power flow/CPF and conformal low power debug.
• Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure
• Good in low power techniques and Conformal Low Power
• Developing CPF/UPF files
• Scripting skills in any programming language (preferably Perl, TCL and Shell)
• Ability in debugging, problem solving and analytical skills.
• Good communication skills

Requirements/Qualifications:

• Bachelors/Masters in Electronics or equivalent degree with 6+ years of experience

Travel Time:

0% - 25%