Senior Engineer, Design Verification

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Marvell Central Engineering (CE) develops Marvell most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production.
Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products.

What You Can Expect

• IP/ASIC design verification engineer responsible for the verification and evaluation of digital circuits in high speed data communication ICs.
• The candidate will be involved in verification plan development, test environment setup, modeling, test-case development and execution.
• He/She will be responsible for block and/or chip level verification and verification of PCIE, Ethernet, Serdes PHY's functions using UVM methodology, System Verilog

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 4-6 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-4 years of experience.
• Strong knowledge of UVM/OVM/VMM.
• Good knowledge of SystemVerilog/Verilog/C/C++/System C.
• Solid background of random techniques, coverage-driven verification environment/flow.
• Strong ability of scripting languages such as Perl, Python, Makefile, C Shell.
• The ability to do Digital-Analog-Mixed simulations and develop UVM AMS models.
• Good personal communication skills and team working spirit. Hardworking and motivated to be part of a highly competent team

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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