Senior Engineer, Analog IC Design

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Santa Clara, CA, USA
In-Office
110K-140K Annually
Senior level
Artificial Intelligence • Automotive • Semiconductor
We create custom semiconductor solutions that move, process, store, and secure data quickly and reliably.
The Role
Design and optimize transistor-level analog IC circuits, perform pre- and post-layout simulations, analyze performance across PVT corners, and validate prototype silicon through laboratory testing. Responsibilities include high-speed receiver/transmitter design, bias circuits, current mirrors, signal integrity analysis, FPGA-to-PC data transfer, PCB test-board debugging, documentation, and collaboration through production handoff.
Summary Generated by Built In

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As an Analog IC Design Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.

What You Can Expect

Design and optimize circuits to meet key performance targets. Build transistor-level circuits from scratch or improve/port existing blocks using tools like Cadence. Run simulations to evaluate various performance metrics and conduct circuit analysis to validate designs. Handoff validated designs for physical layout, then verify post-layout performance through additional simulation and testing. Perform laboratory testing and characterization of prototype silicon to verify functionality and compliance with design specifications. Prepare documentation and support cross-functional development activities as needed. Join weekly team meetings to discuss project progress, share updates, and collaboratively resolve design issues. Present and review work with senior designers and managers, following designs through from concept to production. Wage $110,000.00 - $140,000.00 per year.

What We're Looking For

Bachelor’s or foreign equivalent degree in Electrical Engineering, Materials Science, Physics/ Applied Physics, Computer Engineering, or a related field.

Must have at least three (3) months of work/internship/project experience or completed coursework in each of the following:

• Deep sub-micron CMOS technologies.

• Analog-Digital Interfaces.

• Implementing StrongARM latch comparator for better accuracy and low power consumption and capacitive DAC.

• Using industry CAD tools including Cadence Spectre, SPICE, Verilog, HSPICE, and MATLAB for circuit modeling, analysis, and verification.

• Applying low-power and high-speed design techniques to meet functional, power, and performance requirements.

• FPGA programming and data transfer between FPGA and PC.

• Supporting the design and debugging of laboratory PCB test boards, including power regulation circuits, bias networks, clock distribution components, and high-speed signal routing.

• Designing and analyzing high-speed receiver or transmitter building blocks such as CTLE, VGA, buffer stages, or clock/data recovery circuits.

• Performing pre-layout and post-layout simulations, including parasitic extraction and corner (PVT) analysis.

• Analyzing signal integrity metrics such as jitter, bandwidth, return loss, and eye diagram performance.

• Designing biasing circuits and current mirrors, including mismatch analysis and device sizing considerations.

• Working with high-frequency modeling and layout considerations, including parasitic capacitance, inductance, and EM effects.

This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-TT1

Skills Required

  • Bachelor's degree or foreign equivalent in Electrical Engineering, Materials Science, Physics, Applied Physics, Computer Engineering, or a related field.
  • At least three months of work, internship, project experience, or completed coursework in deep sub-micron CMOS technologies.
  • At least three months of experience or coursework in analog-digital interfaces.
  • Experience implementing StrongARM latch comparators and capacitive DACs.
  • Experience using Cadence Spectre, SPICE, Verilog, HSPICE, and MATLAB for circuit modeling, analysis, and verification.
  • Experience applying low-power and high-speed design techniques.
  • Experience with FPGA programming and data transfer between FPGA and PC.
  • Experience designing and debugging laboratory PCB test boards, including power regulation, bias networks, clock distribution, and high-speed signal routing.
  • Experience designing and analyzing high-speed receiver or transmitter blocks such as CTLE, VGA, buffer stages, or clock/data recovery circuits.
  • Experience performing pre-layout and post-layout simulations, parasitic extraction, and PVT corner analysis.
  • Experience analyzing signal integrity metrics including jitter, bandwidth, return loss, and eye diagrams.
  • Experience designing and analyzing biasing circuits and current mirrors, including mismatch analysis and device sizing.
  • Experience with high-frequency modeling and layout considerations, including parasitic capacitance, inductance, and electromagnetic effects.

Marvell Technology Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Marvell Technology and has not been reviewed or approved by Marvell Technology.

  • Equity Value & Accessibility — Equity appears to be a meaningful part of total rewards through RSUs and an ESPP with a 15% discount and lookback, which can materially raise overall compensation. Stock upside is positioned as a key differentiator when company performance is strong.
  • Parental & Family Support — Paid parental/bonding leave is described as substantial, with additional disability leave for birthing parents and a flexible return-to-work program. Family-care leave, generous bereavement provisions, and family-building support (e.g., adoption/surrogacy reimbursement) further strengthen the package.
  • Healthcare Strength — Medical coverage is presented as broad with multiple plan options and preventive care covered at 100% in-network, alongside dental, vision, and structured mental-health support. Additional programs like telehealth and specialized care partners add depth to the health offering.

Marvell Technology Insights

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The Company
HQ: Santa Clara, CA
6,500 Employees
Year Founded: 1995

What We Do

Marvell specializes in semiconductor solutions that power a wide range of industries, from data centers and 5G networks to AI, automotive, and storage applications. Our cutting-edge products are designed to meet the constantly evolving demands of a connected world, enabling faster, more efficient and more secure data processing and communication. With a focus on excellence and a commitment to advancing technology, we develop solutions that drive progress and transform industries.

Why Work With Us

Life at Marvell means being a part of new innovation and enduring technology; but it's also much more. Our diverse community is strengthened through cultural events, corporate gatherings and team-building activities, fostering collaboration and making work enjoyable. At Marvell, it's not just a job; it's an enriching, community-driven experience.

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