Senior Digital Verification Engineer

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Digital Verification Engineer 
 

Senior Digital Verification Engineer
Austin, TX
The position involves owning verification of critical wireless IP/SS/SoC components using a combination of simulation and formal verification techniques. The qualified candidate should have built C/UVM test benches from scratch and taken them through all stages of execution. The candidate will work with Architects and cross functional teams to deliver comprehensive verification strategy along side system level debug . The candidate will get exposure to AMS and DMS verification in this role to help expand his/her verification knowledge base  

Responsibilities 

•  IP/SS/SoC Verification for breakthrough wireless designs
• Create and execute the test plan with emphasis on metrics driven verification  
• Constrained random tests, scoreboard, and coverage development  
• Power Architecture Verification including low power modes with UPF
• Apply formal verification tools like lint, auto, and property checks  
• DMS , AMS & System Level Verification & Debug ( pre/post silicon )
• GLS & Power Analysis
• Architect and implement Verification Components using C/UVM-based methods 
• Develop verification flows and methodologies to enhance IP, SoC, and Formal Verification 

Skills You Will Need:

• 8+ years in Industry 
• Bachelor's or Master's degree in Electrical/Computer Engineering  
• Strong knowledge of Verilog, SystemVerilog, UVM, and C/C++ 
• Knowledge of digital design, ARM, or RISC-V architecture and bus protocols 
• Knowledge of scripting languages like Perl, Python, Tcl, and shell 
• Advanced verification skill in SVAs, constrained random stimulus, and coverage analysis 
• C-based testcase development and debugging skills 
• Verify and debug low-power design with UPF 

The following qualifications will be considered a plus:  

• Debug SDF Back Annotated Gate Simulations 
• Mentoring and leadership skills 
• Exceptional problem-solving skills  
• Good written and oral communication skills 
   

Benefits & Perks 

You can look forward to the following benefits:   

• Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans
• Highly competitive salary
• 401k plan with match and Roth plan option
• Equity rewards (RSUs)
• Employee Stock Purchase Plan (ESPP)
• Life/AD&D and disability coverage
• Flexible spending accounts
• Adoption assistance
• Back-Up childcare
• Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
• Flexible PTO schedule
• 3 paid volunteer days per year
• Charitable contribution match
• Tuition reimbursement
• Free downtown parking
• Onsite gym
• Monthly wellness offerings
• Free snacks
• Monthly company updates with our CEO
   

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The annualized base pay range for this role is expected to be between $126,000 - $234,000 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.