Senior or Staff Digital Design Engineer
Reports To: Head of Engineering
About Us
Powerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing.
About the Role
We are seeking an experienced and hands-on Senior Digital Design Engineer to contribute to the design and implementation of complex digital systems and SoC components. This role offers the opportunity to own significant functional blocks from microarchitecture through RTL development, integration, and implementation while collaborating closely with verification, physical design, and DFT teams.
The ideal candidate is passionate about digital design, enjoys solving challenging technical problems, and thrives in a collaborative startup environment where individual contributions have a direct impact on product success.
Key Responsibilities
Digital Design & RTL Development
Develop microarchitecture for assigned digital blocks and subsystems
Design, code, and maintain high-quality, synthesizable RTL
Evaluate design tradeoffs involving performance, power, area (PPA), and testability
Participate in design reviews and incorporate feedback into RTL implementation
Integration & Implementation
Integrate RTL into larger subsystem and SoC environments
Support lint, CDC/RDC, synthesis, and design quality checks
Collaborate with physical design teams to resolve implementation issues
Assist with timing constraint development and timing closure activities
Support logic equivalence checking (LEC) and implementation debugging
Participate in functional and timing ECO development when required
Design Quality
Ensure designs meet functional, timing, power, and DFT requirements
Support silicon bring-up, validation, and post-silicon debug activities
Analyze and resolve design issues throughout the development lifecycle
Cross-Functional Collaboration
Work closely with verification, DFT, physical implementation, firmware, and systems teams
Partner with architects and senior technical leaders to refine design requirements
Contribute to continuous improvement of design methodologies and development processes
Mentor junior engineers and share technical knowledge within the team (Staff level)
Qualifications
This is a Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouver and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline
6+ years of digital IC design experience
Strong hands-on RTL development experience using Verilog or SystemVerilog
Experience designing digital blocks for complex SoCs or ASICs
Solid understanding of:
RTL design and microarchitecture
SoC integration and standard on-chip interfaces
Clocking, resets, CDC/RDC methodologies
Synthesis and physical implementation considerations
Timing constraints (SDC) and timing closure
Experience with industry-standard EDA tools (Synopsys and/or Cadence)
Strong debugging, analytical, and problem-solving skills
Excellent communication and collaboration skills
Preferred
Experience with DFT methodologies including scan insertion and MBIST
Experience with logic equivalence checking (LEC)
Familiarity with static timing analysis (STA)
Experience with UPF/CPF low-power methodologies
Exposure to advanced semiconductor process nodes
Experience supporting silicon bring-up and post-silicon debug
Formal verification experience is a plus
Compensation & Benefits
Anticipated annual base salary for Member of Technical Staff: $150,000 - $200,000
Stock option grant
Comprehensive benefits package including health, dental, vision, and 401(k)
Skills Required
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline
- 6+ years of digital IC design experience
- Strong hands-on RTL development experience using Verilog or SystemVerilog
- Experience designing digital blocks for complex SoCs or ASICs
- Understanding of RTL design and microarchitecture
- Understanding of SoC integration and standard on-chip interfaces
- Understanding of clocking, resets, and CDC/RDC methodologies
- Understanding of synthesis and physical implementation considerations
- Understanding of timing constraints using SDC and timing closure
- Experience with industry-standard EDA tools such as Synopsys and/or Cadence
- Strong debugging, analytical, and problem-solving skills
- Excellent communication and collaboration skills
- Experience with DFT methodologies, including scan insertion and MBIST
- Experience with logic equivalence checking
- Familiarity with static timing analysis
- Experience with UPF/CPF low-power methodologies
- Exposure to advanced semiconductor process nodes
- Experience supporting silicon bring-up and post-silicon debug
- Formal verification experience
What We Do
PowerLattice redefines how power enters into processors with its groundbreaking power delivery chiplets. Combining on-die magnetic inductors, advanced micro-IVR circuits, a vertical design and a programmable software layer into a single chiplet die, PowerLattice enables the tightest coupling between power and compute, and delivers the breakthrough performance, efficiency and reliability for AI and data center infrastructure.
