We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.
- Must be able to obtain and maintain a Department of Defense classified clearance
- Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
- Should possess intimate knowledge of DFT insertion flows
- Basic scan chain insertion using synthesis or other software tools
- Experience in compression scan insertion, LBIST and other scan technologies
- Intimate knowledge of memory build-in self-test (MBIST)
- Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
- Debug and Analysis of failures to improve fault coverage
- Verification of ATPG testbenches and debugging root cause of simulation mis-compares
- Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
- Knowledge of timing analysis and equivalency checks would be added bonus
- Ability to work in collaborative team environment
- Prior experience with Cadence tools and flows is highly desirable
- Should be able to finish DFT tasks independently
- Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems
- Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
- Self-driven and committed individual who can work in a fast-paced project environment
Skills Required
- 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
- Intimate knowledge of DFT insertion flows
- Experience in compression scan insertion
- Experience with memory built-in self-test (MBIST)
- Expertise in Automatic Test Pattern Generation (ATPG)
- Ability to maintain a Department of Defense classified clearance
- Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
- Prior experience with Cadence tools and flows is highly desirable
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
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