Job Description:
We are seeking a talented and motivated IP Verification Engineer to join our team. In this role, you will be instrumental in ensuring the functional correctness and quality of our IP blocks for use in complex SoCs (System on a Chip) and FPGAs (Field Programmable Gate Arrays). You will collaborate closely with architecture, design, software, and validation teams to achieve first-pass success.
Qualifications:Key Responsibilities
Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.
Develop verification components, including drivers, monitors, scoreboards, and checkers.
Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties.
Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.
Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.
Develop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows.
Participate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback.
Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or a related field.
10+ years of experience in ASIC or FPGA design verification.
Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog.
Strong hands-on experience in developing UVM-based testbenches and verification components.
Proficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV).
Familiarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet is a plus.
Experience with simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
Strong scripting skills in Python, Perl, or Tcl for automation and data analysis.
Excellent analytical, problem-solving, and debugging skills.
Strong communication skills and the ability to work effectively in a collaborative, cross-functional team environment.
Skills Required
- Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or related field
- 10+ years of experience in ASIC or FPGA design verification
- Expertise in Hardware Description Languages: Verilog or VHDL and SystemVerilog
- Hands-on experience developing UVM-based testbenches and verification components
- Proficiency in coverage-driven verification (CDV) and assertion-based verification (ABV)
- Experience using SystemVerilog Assertions (SVA) and formal verification methods
- Experience with simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)
- Strong scripting skills for automation and data analysis in Python, Perl, or Tcl
- Familiarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet
- Excellent analytical, problem-solving, debugging, communication, and cross-functional collaboration skills
Altera (altera.com) Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).
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Retirement Support — Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
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Leave & Time Off Breadth — Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
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Parental & Family Support — Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.
Altera (altera.com) Insights
What We Do
Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
