Altera is responsible for High-Speed Protocol IP development, which includes participating in high-level product specifications, logic/RTL design and implementation, RTL verification, IP FPGA validation and debugging.
As Lead DV Engineer focusing on IP Verification & Validation, you will be responsible for carrying out design validation for Altera next generation IP's across the Altera FPGA IP product portfolios. The charter of IP verification & validation team is to verify and validate the IP for robust functionality from functional simulation. The verification and validation areas encompass IP's for high-speed transceiver protocols (Preferred – Ethernet/PCIe/CXL).
Create comprehensive verification and validation plan based on IP/FPGA architecture specifications and carry out all the IP validation tasks. The plan encompasses functional, system level and hardware verification and validation perspectives.
Developing IP/subsystem/system level testbench, create tests, and necessary coverage goals based on specification to verify the implementation. Writing directed and random test cases, debugging failures, filing and closing bugs.
Review verification and validation results against the coverage goals. Writing, analyzing and achieving coverage metrics.
Work with cross-functional teams and prepare/support IP functional validation tests for IP bring-up on actual FPGA development kits.
Creating and establishing IP subsystem/solution validation coverage strategy and standardized framework, drive system test design implementation and overall IP system validation on HW, maximizing FPGA hardware capability to bring substantial improvement to IP quality & usability for Altera FPGA IP product portfolios.
Developing verification and validation tools and flows, as needed.
Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time-to-market.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$142.6k - $206.5k USD
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Qualifications:Minimum Qualifications:
BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study and 9+ years of industry experience.
9+ years of experience developing verification collateral in Verilog, System Verilog and UVM
7+ years with Ethernet/PCIe/CXL protocol verification is required
7+ years in UVM Fluency is a must
7+ years of complex coverage driven random constraint UVM environments
7+ years of experience with High level Specification into test plan and developing tests cases
7+ years of experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required
Good communication skills
Top Skills
What We Do
Altera: Accelerating Innovators
Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
