Senior Design Technology Co-Optimization (DTCO) Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Collaborate with internal teams and external partners to increase DTCO activities, including projects with Intel, Rapidus, Samsung, and TSMC.
• Conduct simulations and analysis on parametrics, aging, BTI, HCI, and reliability.
• Support the development of future IP NRE contracts with major semiconductor companies.
• Address critical gaps in silicon validation, package/board design, and controller teams.
• Utilize budget effectively to fill critical roles and support ongoing projects.
• Provide technical expertise and guidance to junior engineers and team members.

Qualifications:

• Proven experience in DTCO, reliability modeling, and noise/overdrive analysis.
• Strong background in AMS, FIP designs, and security IPs.
• Previous experience working with leading semiconductor companies such as Intel and Synopsys.
• Excellent problem-solving skills and ability to work in a fast-paced environment.
• Strong communication and collaboration skills.

Preferred Qualifications:

• Experience with FIVR, AMS Security IPs, GPIO, and other related technologies.
• Familiarity with PDK evaluations and multiple DIP teams (Memory, UCiE, SerDes).
• Ability to manage multiple projects and prioritize tasks effectively.

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