SENIOR DESIGN ENGR

Posted One Month Ago
Be an Early Applicant
2 Locations
In-Office
Senior level
Automotive • Internet of Things • Mobile • Semiconductor • Industrial
The Role
Design and verify high-performance, low-power, reliable RISC-V CPU cores for edge-product SoCs. Responsibilities include defining microarchitecture, developing RTL, optimizing pipelining and PPA, analyzing performance, collaborating with physical design, creating C and assembly test cases, and leading verification signoff using UVM, assertions, formal verification, coverage, test plans, and regression management.
Summary Generated by Built In

Role Overview

Design and Verify high-performance, low-power, high-reliability RISC‑V CPU cores for SoCs used in various edge products like automotive, IoT and mobile. Focus on microarchitecture, pipelining, and PPA (performance/power/area) optimization, with strong emphasis on functional safety and predictable performance. Deliver the first pass success of complex  RISC-V CPU IPs using the latest advanced verification languages and methodology.

Key Responsibilities

  • Define and implement CPU microarchitecture (pipeline, execution units, control, ISA features)
  • Design efficient pipelined cores with robust hazard handling and latency/throughput optimization
  • Drive PPA trade-offs (frequency, area, power, determinism) across design stages
  • Develop and debug RTL (SystemVerilog/Verilog); support verification and bring-up; perform various design checks
  • Perform performance analysis / bottleneck identification and drive optimizations
  • Collaborate with physical design to meet timing, power, and area targets
  • Code assembly level and C testcases to verify the core
  • Drive (or participate in) the verification signoff using methodologies notably assembly language, UVM, assertions and formal verification.
  • Carry out a thorough analysis of existing defects, change requests and new features and develop related Testbench components and execute Test plan for the core.
  • Shall be capable to own & perform the complete sign off process for the core modules including 100% Code & Functional Coverage targets, Assertions, writing and updating test plans, Verification Guides, regression management etc.

More information about NXP in India...

#LI-2734

Skills Required

  • Experience defining and implementing CPU microarchitecture, including pipelines, execution units, control, and ISA features
  • Experience designing pipelined CPU cores with hazard handling and latency and throughput optimization
  • Experience developing and debugging RTL using SystemVerilog and Verilog
  • Experience with performance, power, and area optimization
  • Experience coding C and assembly-level test cases
  • Experience with UVM, assertions, and formal verification
  • Experience with verification signoff, code and functional coverage, test plans, regression management, and verification guides
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The Company
HQ: Eindhoven
21,993 Employees
Year Founded: 2006

What We Do

NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 34,500 employees in more than 30 countries and posted revenue of $13.21 billion in 2022. Find out more at www.nxp.com. Privacy Policy: https://www.nxp.com/company/about-nxp/privacy-policy-for-social-media-pages:PRIVACY-POLICY-SOCIAL-MEDIA

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