The Role and Impact
Join Intel's Design Technology Platform (DTP) organization and become an integral part of a highly skilled team driving the development of cutting-edge technologies. As an EDA Tools Software Engineer, you will design, develop, test, and debug software tools and methodologies that directly support Intel's hardware product design and manufacturing processes. Your work will enable design teams to innovate faster, meet complex manufacturability constraints, and deliver industry-leading products to market. By contributing to Intel's advanced process technologies, you will play a pivotal role in achieving leadership in design automation and fostering a culture of innovation.
Key Responsibilities
Design, develop, and debug Fill components of Process Design Kits (PDKs),
Provide algorithmic solutions using tools such as Calibre, ICV, and Pegasus to address density deficiencies and ensure manufacturability compliance.
Collaborate with process developers, design rule owners, and end users to define requirements and implement state-of-the-art solutions.
Automate workflows to enhance efficiency, accuracy, and deployment across design teams.
Develop comprehensive test cases and systems to validate software tools and ensure seamless integration with various design methodologies.
Innovate and drive advancements in EDA tools and methodologies to meet the evolving needs of Intel's technology ecosystem.
Partner with cross-functional teams and external EDA vendors to define and implement new tool features and methodologies.
Maintain documentation, including training materials and user guides, to support customers and ensure robust deployment.
In this role, you will have a unique opportunity to make a lasting impact by enabling Intel's success in the competitive semiconductor landscape. Take the next step in your career and join a team where your expertise will help shape the future of technology innovation.
Qualifications:Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of experience, Master's degree with 5+ years of experience, or PhD with 2+ years of experience.
Minimum 5 years of hands-on experience with at least one industry-standard physical verification platform (Calibre, ICV, or Pegasus), including methodology development, rule deck debugging, or production deployment.
3+ years of direct experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, or PVL/PVTCL for DRC, density, or fill verification applications.
Solid understanding of semiconductor device physics, process technology, and design rules.
Experience in developing algorithmic solutions for physical design challenges in advanced manufacturing nodes.
Strong knowledge of Unix/Linux platforms and computing environments.
Preferred Qualifications
5+ years of hands-on experience developing, deploying, or supporting density fill methodologies for semiconductor technologies at 16nm and below, including ownership of fill rule implementation, density compliance, or manufacturability optimization.
Experience with advanced physical verification techniques, including DRC, and density/fill modules.
Industry experience with other foundry technologies in this domain is strongly desirable
Familiarity with custom layout tools such as Cadence Virtuoso or Synopsys Custom Designer.
Deep understanding of technology scaling challenges and their impact on physical design rules.
Proven track record of collaborating across multiple internal and external teams to deliver optimal solutions.
Exceptional analytical and problem-solving skills with the ability to address cross-disciplinary challenges.
Strong written and verbal communication skills, with the ability to present complex technical concepts clearly.
Leadership experience driving innovation, process improvements, or cross-functional initiatives.
Strong preference for candidates with experience from semiconductor foundries, advanced packaging organizations (OSATs), integrated device manufacturers (IDMs), or EDA vendors, where they have contributed to physical verification, density-fill methodology development, process design kits (PDKs), or manufacturing-driven design solutions.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, AustinPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Skills Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 8+ years experience; Master's with 5+ years; or PhD with 2+ years.
- Minimum 5 years hands-on experience with at least one physical verification platform (Calibre, ICV, or Pegasus), including methodology development, rule deck debugging, or production deployment.
- 3+ years direct experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, or PVL/PVTCL for DRC, density, or fill verification.
- Solid understanding of semiconductor device physics, process technology, and design rules.
- Experience developing algorithmic solutions for physical design challenges in advanced manufacturing nodes.
- Strong knowledge of Unix/Linux platforms and computing environments.
- 5+ years hands-on experience developing, deploying, or supporting density fill methodologies for semiconductor technologies at 16nm and below (preferred).
- Experience with advanced physical verification techniques, including DRC and density/fill modules.
- Industry experience with other foundry technologies in this domain (preferred).
- Familiarity with custom layout tools such as Cadence Virtuoso or Synopsys Custom Designer.
- Deep understanding of technology scaling challenges and their impact on physical design rules.
- Proven track record of collaborating across internal and external teams to deliver solutions.
- Exceptional analytical and problem-solving skills and strong written and verbal communication.
- Leadership experience driving innovation, process improvements, or cross-functional initiatives.
- Preference for candidates with experience from semiconductor foundries, OSATs, IDMs, or EDA vendors in relevant domains.
Intel Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.
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Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
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Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
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Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.
Intel Insights
What We Do
Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.
