As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
Role Summary
We are seeking a Senior Design Formal Verification Engineer to own formal strategies for advanced out‑of‑order (OoO) CPU cores. You will work closely with micro‑architects and RTL designers to verify complex execution pipelines.
Responsibilities:
• Identify blocks suitable for applying Formal Verification
• Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics
• Implementation and maintenance of Formal Verification environments in Chisel
• Applying various FV techniques to reduce complexity and prove correctness of DUT
• Debugging RTL to identify causes of failure scenarios
• Guide and train team members on effective usage of Formal Verification tools
• Develop/modify scripts to automate the verification process
• Review formal setups and proofs with design and verification teams
• Maintain and extend assertion libraries
Requirements:
- 5+ years of experience in Formal Verification of Digital Hardware Design
- Extensive experience with Formal Abstraction Techniques and sign-off process
- Familiarity with industry-standard Formal Verification Tools, such as VC Formal, JasperGold
- Knowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ SystemVerilog
- Knowledge of Object-oriented Programming is a plus
- A keen interest in Processors and Digital systems
- Strong reasoning skills and excellent attention to detail
- Good inter-personal and teamwork skills!
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
IndiaAny offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Skills Required
- 5+ years of experience in formal verification of digital hardware design
- Extensive experience with formal abstraction techniques and the sign-off process
- Familiarity with industry-standard formal verification tools such as VC Formal and JasperGold
- Knowledge of hardware description and verification languages such as VHDL, Verilog, or SystemVerilog
- Knowledge of object-oriented programming
- Interest in processors and digital systems
- Strong reasoning skills and excellent attention to detail
- Good interpersonal and teamwork skills
What We Do
The heart of SiFive is RISC-V! SiFive creates the building blocks of RISC-V-based IP that are the inevitable innovative reimagining of every computing platform.
