Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
We are looking for Senior ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc. This is an opportunity to contribute hands-on technical expertise within Astera Labs’ hyper-growth connectivity business and help deliver purpose-built solutions that scale with the demands of rack-scale AI systems.
Basic Qualifications
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
- ≥2 year experience releasing complex SoC/silicon products to high volume manufacturing.
- Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
- Professional attitude with ability to execute on multiple tasks with minimal supervision.
- Strong team player with good communication skills to work alongside a team of high caliber engineers.
- Entrepreneurial, open-mind behavior and can-do attitude.
Required Experience
- Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
- Collaboration with design team to define test strategy, create and own test plan.
- Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
- Familiar with high-speed load board design techniques.
- Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
- Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
- Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.
- Expertise in production test of high speed SerDes operating at 16Gbps and higher.
- Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
- Experience with lab equipment including protocol analyzers and oscilloscopes.
- Experience with using Advantest 93k ATE platform.
- Proficiency in, at least, one modern programming language such as C/C++, Python.
Preferred Experience
- Fluent in data processing using high level programming languages.
- Experience in running External loopback at wafer sort.
- Familiarity with modern databases
Salary range is $135,500 to $170,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Skills Required
- Bachelor's degree in Electrical Engineering
- Master's degree in Electrical Engineering
- At least 2 years of experience releasing complex SoC or silicon products to high-volume manufacturing
- Hands-on experience developing high-speed mixed-signal SoC test programs and hardware on multiple high-speed test platforms
- Experience defining test strategy and owning test plans with design teams
- Experience selecting tester platforms and developing ATE hardware for wafer sort and final test
- Experience with high-speed load board design
- Experience implementing ATE patterns to optimize tester resources and minimize test time while maintaining product quality
- Strong knowledge of DFT techniques including SCAN, MEMBIST, SerDes, and functional tests
- Experience with I2C, I3C, SPI, MDIO, and JTAG control interfaces
- Experience with production testing of high-speed SerDes operating at 16 Gbps or higher
- Experience with ATE programming, silicon/ATE bring-up, bench-ATE correlation, and debug
- Experience using protocol analyzers and oscilloscopes
- Experience with the Advantest 93k ATE platform
- Proficiency in at least one modern programming language such as C/C++ or Python
- Experience with high-level programming languages for data processing
- Experience running external loopback at wafer sort
- Familiarity with modern databases
Astera Labs Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Astera Labs and has not been reviewed or approved by Astera Labs.
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Healthcare Strength — Health plans are described as competitive and employer-subsidized, covering medical, dental, and vision for employees and dependents. Company materials and listings consistently emphasize strong core healthcare coverage.
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Leave & Time Off Breadth — Flexible time off is highlighted alongside paid company holidays, with guidance indicating generous PTO when coordinated with teams. Documented policies also point to robust time-off structures across locations.
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Equity Value & Accessibility — Stock-based compensation is a meaningful part of total pay, with RSUs and an employee stock purchase plan noted as part of the package. Public-company status enhances perceived value and accessibility of equity components.
Astera Labs Insights
What We Do
Astera Labs Inc., a fabless semiconductor company headquartered in the heart of California’s Silicon Valley, is a leader in purpose-built connectivity solutions for data-centric systems throughout the data center. Partnering with leading processor vendors, cloud service providers, seasoned investors, and world-class manufacturing companies, Astera Labs is helping customers remove performance bottlenecks in data-intensive systems that are limiting the true potential of applications such as artificial intelligence and machine learning. The company’s product portfolio includes system-aware semiconductor integrated circuits, boards, and services to enable robust CXL, PCIe, and Ethernet connectivity.
